1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * setup.c - boot time setup code 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include <linux/init.h> 7*4882a593Smuzhiyun #include <linux/export.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/bootinfo.h> 10*4882a593Smuzhiyun #include <asm/reboot.h> 11*4882a593Smuzhiyun #include <asm/time.h> 12*4882a593Smuzhiyun #include <linux/ioport.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <asm/mach-rc32434/rb.h> 15*4882a593Smuzhiyun #include <asm/mach-rc32434/pci.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct pci_reg __iomem *pci_reg; 18*4882a593Smuzhiyun EXPORT_SYMBOL(pci_reg); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun static struct resource pci0_res[] = { 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun .name = "pci_reg0", 23*4882a593Smuzhiyun .start = PCI0_BASE_ADDR, 24*4882a593Smuzhiyun .end = PCI0_BASE_ADDR + sizeof(struct pci_reg), 25*4882a593Smuzhiyun .flags = IORESOURCE_MEM, 26*4882a593Smuzhiyun } 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun rb_machine_restart(char * command)29*4882a593Smuzhiyunstatic void rb_machine_restart(char *command) 30*4882a593Smuzhiyun { 31*4882a593Smuzhiyun /* just jump to the reset vector */ 32*4882a593Smuzhiyun writel(0x80000001, IDT434_REG_BASE + RST); 33*4882a593Smuzhiyun ((void (*)(void)) KSEG1ADDR(0x1FC00000u))(); 34*4882a593Smuzhiyun } 35*4882a593Smuzhiyun rb_machine_halt(void)36*4882a593Smuzhiyunstatic void rb_machine_halt(void) 37*4882a593Smuzhiyun { 38*4882a593Smuzhiyun for (;;) 39*4882a593Smuzhiyun continue; 40*4882a593Smuzhiyun } 41*4882a593Smuzhiyun plat_mem_setup(void)42*4882a593Smuzhiyunvoid __init plat_mem_setup(void) 43*4882a593Smuzhiyun { 44*4882a593Smuzhiyun u32 val; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun _machine_restart = rb_machine_restart; 47*4882a593Smuzhiyun _machine_halt = rb_machine_halt; 48*4882a593Smuzhiyun pm_power_off = rb_machine_halt; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun set_io_port_base(KSEG1); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pci_reg = ioremap(pci0_res[0].start, 53*4882a593Smuzhiyun pci0_res[0].end - pci0_res[0].start); 54*4882a593Smuzhiyun if (!pci_reg) { 55*4882a593Smuzhiyun printk(KERN_ERR "Could not remap PCI registers\n"); 56*4882a593Smuzhiyun return; 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun val = __raw_readl(&pci_reg->pcic); 60*4882a593Smuzhiyun val &= 0xFFFFFF7; 61*4882a593Smuzhiyun __raw_writel(val, (void *)&pci_reg->pcic); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifdef CONFIG_PCI 64*4882a593Smuzhiyun /* Enable PCI interrupts in EPLD Mask register */ 65*4882a593Smuzhiyun *epld_mask = 0x0; 66*4882a593Smuzhiyun *(epld_mask + 1) = 0x0; 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun write_c0_wired(0); 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun get_system_type(void)71*4882a593Smuzhiyunconst char *get_system_type(void) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun switch (mips_machtype) { 74*4882a593Smuzhiyun case MACH_MIKROTIK_RB532A: 75*4882a593Smuzhiyun return "Mikrotik RB532A"; 76*4882a593Smuzhiyun break; 77*4882a593Smuzhiyun default: 78*4882a593Smuzhiyun return "Mikrotik RB532"; 79*4882a593Smuzhiyun break; 80*4882a593Smuzhiyun } 81*4882a593Smuzhiyun } 82