xref: /OK3568_Linux_fs/kernel/arch/mips/rb532/irq.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *  This program is free software; you can redistribute  it and/or modify it
3*4882a593Smuzhiyun  *  under  the terms of  the GNU General  Public License as published by the
4*4882a593Smuzhiyun  *  Free Software Foundation;  either version 2 of the  License, or (at your
5*4882a593Smuzhiyun  *  option) any later version.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8*4882a593Smuzhiyun  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9*4882a593Smuzhiyun  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10*4882a593Smuzhiyun  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
11*4882a593Smuzhiyun  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12*4882a593Smuzhiyun  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
13*4882a593Smuzhiyun  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14*4882a593Smuzhiyun  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
15*4882a593Smuzhiyun  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16*4882a593Smuzhiyun  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  *  You should have received a copy of the  GNU General Public License along
19*4882a593Smuzhiyun  *  with this program; if not, write  to the Free Software Foundation, Inc.,
20*4882a593Smuzhiyun  *  675 Mass Ave, Cambridge, MA 02139, USA.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * Copyright 2002 MontaVista Software Inc.
23*4882a593Smuzhiyun  * Author: MontaVista Software, Inc.
24*4882a593Smuzhiyun  *		stevel@mvista.com or source@mvista.com
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include <linux/bitops.h>
28*4882a593Smuzhiyun #include <linux/errno.h>
29*4882a593Smuzhiyun #include <linux/init.h>
30*4882a593Smuzhiyun #include <linux/io.h>
31*4882a593Smuzhiyun #include <linux/kernel_stat.h>
32*4882a593Smuzhiyun #include <linux/signal.h>
33*4882a593Smuzhiyun #include <linux/sched.h>
34*4882a593Smuzhiyun #include <linux/types.h>
35*4882a593Smuzhiyun #include <linux/interrupt.h>
36*4882a593Smuzhiyun #include <linux/ioport.h>
37*4882a593Smuzhiyun #include <linux/timex.h>
38*4882a593Smuzhiyun #include <linux/random.h>
39*4882a593Smuzhiyun #include <linux/delay.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #include <asm/bootinfo.h>
42*4882a593Smuzhiyun #include <asm/time.h>
43*4882a593Smuzhiyun #include <asm/mipsregs.h>
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #include <asm/mach-rc32434/irq.h>
46*4882a593Smuzhiyun #include <asm/mach-rc32434/gpio.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct intr_group {
49*4882a593Smuzhiyun 	u32 mask;	/* mask of valid bits in pending/mask registers */
50*4882a593Smuzhiyun 	volatile u32 *base_addr;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define RC32434_NR_IRQS	 (GROUP4_IRQ_BASE + 32)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #if (NR_IRQS < RC32434_NR_IRQS)
56*4882a593Smuzhiyun #error Too little irqs defined. Did you override <asm/irq.h> ?
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
60*4882a593Smuzhiyun 	{
61*4882a593Smuzhiyun 		.mask	= 0x0000efff,
62*4882a593Smuzhiyun 		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
63*4882a593Smuzhiyun 	{
64*4882a593Smuzhiyun 		.mask	= 0x00001fff,
65*4882a593Smuzhiyun 		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
66*4882a593Smuzhiyun 	{
67*4882a593Smuzhiyun 		.mask	= 0x00000007,
68*4882a593Smuzhiyun 		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
69*4882a593Smuzhiyun 	{
70*4882a593Smuzhiyun 		.mask	= 0x0003ffff,
71*4882a593Smuzhiyun 		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
72*4882a593Smuzhiyun 	{
73*4882a593Smuzhiyun 		.mask	= 0xffffffff,
74*4882a593Smuzhiyun 		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define READ_PEND(base) (*(base))
78*4882a593Smuzhiyun #define READ_MASK(base) (*(base + 2))
79*4882a593Smuzhiyun #define WRITE_MASK(base, val) (*(base + 2) = (val))
80*4882a593Smuzhiyun 
irq_to_group(unsigned int irq_nr)81*4882a593Smuzhiyun static inline int irq_to_group(unsigned int irq_nr)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	return (irq_nr - GROUP0_IRQ_BASE) >> 5;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
group_to_ip(unsigned int group)86*4882a593Smuzhiyun static inline int group_to_ip(unsigned int group)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	return group + 2;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
enable_local_irq(unsigned int ip)91*4882a593Smuzhiyun static inline void enable_local_irq(unsigned int ip)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	int ipnum = 0x100 << ip;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	set_c0_status(ipnum);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun 
disable_local_irq(unsigned int ip)98*4882a593Smuzhiyun static inline void disable_local_irq(unsigned int ip)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	int ipnum = 0x100 << ip;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	clear_c0_status(ipnum);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
ack_local_irq(unsigned int ip)105*4882a593Smuzhiyun static inline void ack_local_irq(unsigned int ip)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	int ipnum = 0x100 << ip;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	clear_c0_cause(ipnum);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
rb532_enable_irq(struct irq_data * d)112*4882a593Smuzhiyun static void rb532_enable_irq(struct irq_data *d)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	unsigned int group, intr_bit, irq_nr = d->irq;
115*4882a593Smuzhiyun 	int ip = irq_nr - GROUP0_IRQ_BASE;
116*4882a593Smuzhiyun 	volatile unsigned int *addr;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	if (ip < 0)
119*4882a593Smuzhiyun 		enable_local_irq(irq_nr);
120*4882a593Smuzhiyun 	else {
121*4882a593Smuzhiyun 		group = ip >> 5;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 		ip &= (1 << 5) - 1;
124*4882a593Smuzhiyun 		intr_bit = 1 << ip;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 		enable_local_irq(group_to_ip(group));
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 		addr = intr_group[group].base_addr;
129*4882a593Smuzhiyun 		WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
rb532_disable_irq(struct irq_data * d)133*4882a593Smuzhiyun static void rb532_disable_irq(struct irq_data *d)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	unsigned int group, intr_bit, mask, irq_nr = d->irq;
136*4882a593Smuzhiyun 	int ip = irq_nr - GROUP0_IRQ_BASE;
137*4882a593Smuzhiyun 	volatile unsigned int *addr;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	if (ip < 0) {
140*4882a593Smuzhiyun 		disable_local_irq(irq_nr);
141*4882a593Smuzhiyun 	} else {
142*4882a593Smuzhiyun 		group = ip >> 5;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 		ip &= (1 << 5) - 1;
145*4882a593Smuzhiyun 		intr_bit = 1 << ip;
146*4882a593Smuzhiyun 		addr = intr_group[group].base_addr;
147*4882a593Smuzhiyun 		mask = READ_MASK(addr);
148*4882a593Smuzhiyun 		mask |= intr_bit;
149*4882a593Smuzhiyun 		WRITE_MASK(addr, mask);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 		/* There is a maximum of 14 GPIO interrupts */
152*4882a593Smuzhiyun 		if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
153*4882a593Smuzhiyun 			rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 		/*
156*4882a593Smuzhiyun 		 * if there are no more interrupts enabled in this
157*4882a593Smuzhiyun 		 * group, disable corresponding IP
158*4882a593Smuzhiyun 		 */
159*4882a593Smuzhiyun 		if (mask == intr_group[group].mask)
160*4882a593Smuzhiyun 			disable_local_irq(group_to_ip(group));
161*4882a593Smuzhiyun 	}
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
rb532_mask_and_ack_irq(struct irq_data * d)164*4882a593Smuzhiyun static void rb532_mask_and_ack_irq(struct irq_data *d)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	rb532_disable_irq(d);
167*4882a593Smuzhiyun 	ack_local_irq(group_to_ip(irq_to_group(d->irq)));
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
rb532_set_type(struct irq_data * d,unsigned type)170*4882a593Smuzhiyun static int rb532_set_type(struct irq_data *d,  unsigned type)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
173*4882a593Smuzhiyun 	int group = irq_to_group(d->irq);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
176*4882a593Smuzhiyun 		return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	switch (type) {
179*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_HIGH:
180*4882a593Smuzhiyun 		rb532_gpio_set_ilevel(1, gpio);
181*4882a593Smuzhiyun 		break;
182*4882a593Smuzhiyun 	case IRQ_TYPE_LEVEL_LOW:
183*4882a593Smuzhiyun 		rb532_gpio_set_ilevel(0, gpio);
184*4882a593Smuzhiyun 		break;
185*4882a593Smuzhiyun 	default:
186*4882a593Smuzhiyun 		return -EINVAL;
187*4882a593Smuzhiyun 	}
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun static struct irq_chip rc32434_irq_type = {
193*4882a593Smuzhiyun 	.name		= "RB532",
194*4882a593Smuzhiyun 	.irq_ack	= rb532_disable_irq,
195*4882a593Smuzhiyun 	.irq_mask	= rb532_disable_irq,
196*4882a593Smuzhiyun 	.irq_mask_ack	= rb532_mask_and_ack_irq,
197*4882a593Smuzhiyun 	.irq_unmask	= rb532_enable_irq,
198*4882a593Smuzhiyun 	.irq_set_type	= rb532_set_type,
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
arch_init_irq(void)201*4882a593Smuzhiyun void __init arch_init_irq(void)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	int i;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	for (i = 0; i < RC32434_NR_IRQS; i++)
208*4882a593Smuzhiyun 		irq_set_chip_and_handler(i, &rc32434_irq_type,
209*4882a593Smuzhiyun 					 handle_level_irq);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun /* Main Interrupt dispatcher */
plat_irq_dispatch(void)213*4882a593Smuzhiyun asmlinkage void plat_irq_dispatch(void)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	unsigned int ip, pend, group;
216*4882a593Smuzhiyun 	volatile unsigned int *addr;
217*4882a593Smuzhiyun 	unsigned int cp0_cause = read_c0_cause() & read_c0_status();
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	if (cp0_cause & CAUSEF_IP7) {
220*4882a593Smuzhiyun 		do_IRQ(7);
221*4882a593Smuzhiyun 	} else {
222*4882a593Smuzhiyun 		ip = (cp0_cause & 0x7c00);
223*4882a593Smuzhiyun 		if (ip) {
224*4882a593Smuzhiyun 			group = 21 + (fls(ip) - 32);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 			addr = intr_group[group].base_addr;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 			pend = READ_PEND(addr);
229*4882a593Smuzhiyun 			pend &= ~READ_MASK(addr);	/* only unmasked interrupts */
230*4882a593Smuzhiyun 			pend = 39 + (fls(pend) - 32);
231*4882a593Smuzhiyun 			do_IRQ((group << 5) + pend);
232*4882a593Smuzhiyun 		}
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun }
235