xref: /OK3568_Linux_fs/kernel/arch/mips/ralink/early_printk.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/serial_reg.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <asm/addrspace.h>
11*4882a593Smuzhiyun #include <asm/setup.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #ifdef CONFIG_SOC_RT288X
14*4882a593Smuzhiyun #define EARLY_UART_BASE		0x300c00
15*4882a593Smuzhiyun #define CHIPID_BASE		0x300004
16*4882a593Smuzhiyun #elif defined(CONFIG_SOC_MT7621)
17*4882a593Smuzhiyun #define EARLY_UART_BASE		0x1E000c00
18*4882a593Smuzhiyun #define CHIPID_BASE		0x1E000004
19*4882a593Smuzhiyun #else
20*4882a593Smuzhiyun #define EARLY_UART_BASE		0x10000c00
21*4882a593Smuzhiyun #define CHIPID_BASE		0x10000004
22*4882a593Smuzhiyun #endif
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define MT7628_CHIP_NAME1	0x20203832
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define UART_REG_TX		0x04
27*4882a593Smuzhiyun #define UART_REG_LCR		0x0c
28*4882a593Smuzhiyun #define UART_REG_LSR		0x14
29*4882a593Smuzhiyun #define UART_REG_LSR_RT2880	0x1c
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
32*4882a593Smuzhiyun static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
33*4882a593Smuzhiyun static int init_complete;
34*4882a593Smuzhiyun 
uart_w32(u32 val,unsigned reg)35*4882a593Smuzhiyun static inline void uart_w32(u32 val, unsigned reg)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	__raw_writel(val, uart_membase + reg);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun 
uart_r32(unsigned reg)40*4882a593Smuzhiyun static inline u32 uart_r32(unsigned reg)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	return __raw_readl(uart_membase + reg);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
soc_is_mt7628(void)45*4882a593Smuzhiyun static inline int soc_is_mt7628(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	return IS_ENABLED(CONFIG_SOC_MT7620) &&
48*4882a593Smuzhiyun 		(__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
find_uart_base(void)51*4882a593Smuzhiyun static void find_uart_base(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	int i;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	if (!soc_is_mt7628())
56*4882a593Smuzhiyun 		return;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	for (i = 0; i < 3; i++) {
59*4882a593Smuzhiyun 		u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 		if (!reg)
62*4882a593Smuzhiyun 			continue;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 		uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE +
65*4882a593Smuzhiyun 							  (0x100 * i));
66*4882a593Smuzhiyun 		break;
67*4882a593Smuzhiyun 	}
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
prom_putchar(char ch)70*4882a593Smuzhiyun void prom_putchar(char ch)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	if (!init_complete) {
73*4882a593Smuzhiyun 		find_uart_base();
74*4882a593Smuzhiyun 		init_complete = 1;
75*4882a593Smuzhiyun 	}
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
78*4882a593Smuzhiyun 		uart_w32((unsigned char)ch, UART_TX);
79*4882a593Smuzhiyun 		while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
80*4882a593Smuzhiyun 			;
81*4882a593Smuzhiyun 	} else {
82*4882a593Smuzhiyun 		while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
83*4882a593Smuzhiyun 			;
84*4882a593Smuzhiyun 		uart_w32((unsigned char)ch, UART_REG_TX);
85*4882a593Smuzhiyun 		while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
86*4882a593Smuzhiyun 			;
87*4882a593Smuzhiyun 	}
88*4882a593Smuzhiyun }
89