xref: /OK3568_Linux_fs/kernel/arch/mips/ralink/clk.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5*4882a593Smuzhiyun  *  Copyright (C) 2013 John Crispin <john@phrozen.org>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/export.h>
11*4882a593Smuzhiyun #include <linux/clkdev.h>
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <asm/time.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include "common.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun struct clk {
19*4882a593Smuzhiyun 	struct clk_lookup cl;
20*4882a593Smuzhiyun 	unsigned long rate;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun 
ralink_clk_add(const char * dev,unsigned long rate)23*4882a593Smuzhiyun void ralink_clk_add(const char *dev, unsigned long rate)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun 	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	if (!clk)
28*4882a593Smuzhiyun 		panic("failed to add clock");
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	clk->cl.dev_id = dev;
31*4882a593Smuzhiyun 	clk->cl.clk = clk;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	clk->rate = rate;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	clkdev_add(&clk->cl);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun  * Linux clock API
40*4882a593Smuzhiyun  */
clk_enable(struct clk * clk)41*4882a593Smuzhiyun int clk_enable(struct clk *clk)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_enable);
46*4882a593Smuzhiyun 
clk_disable(struct clk * clk)47*4882a593Smuzhiyun void clk_disable(struct clk *clk)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_disable);
51*4882a593Smuzhiyun 
clk_get_rate(struct clk * clk)52*4882a593Smuzhiyun unsigned long clk_get_rate(struct clk *clk)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	if (!clk)
55*4882a593Smuzhiyun 		return 0;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	return clk->rate;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_get_rate);
60*4882a593Smuzhiyun 
clk_set_rate(struct clk * clk,unsigned long rate)61*4882a593Smuzhiyun int clk_set_rate(struct clk *clk, unsigned long rate)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	return -1;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_set_rate);
66*4882a593Smuzhiyun 
clk_round_rate(struct clk * clk,unsigned long rate)67*4882a593Smuzhiyun long clk_round_rate(struct clk *clk, unsigned long rate)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	return -1;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_round_rate);
72*4882a593Smuzhiyun 
plat_time_init(void)73*4882a593Smuzhiyun void __init plat_time_init(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	struct clk *clk;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	ralink_of_remap();
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	ralink_clk_init();
80*4882a593Smuzhiyun 	clk = clk_get_sys("cpu", NULL);
81*4882a593Smuzhiyun 	if (IS_ERR(clk))
82*4882a593Smuzhiyun 		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
83*4882a593Smuzhiyun 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
84*4882a593Smuzhiyun 	mips_hpt_frequency = clk_get_rate(clk) / 2;
85*4882a593Smuzhiyun 	clk_put(clk);
86*4882a593Smuzhiyun 	timer_probe();
87*4882a593Smuzhiyun }
88