xref: /OK3568_Linux_fs/kernel/arch/mips/pci/pci.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
5*4882a593Smuzhiyun  * Copyright (C) 2011 Wind River Systems,
6*4882a593Smuzhiyun  *   written by Ralf Baechle (ralf@linux-mips.org)
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #include <linux/bug.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/mm.h>
11*4882a593Smuzhiyun #include <linux/memblock.h>
12*4882a593Smuzhiyun #include <linux/export.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/of_address.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <asm/cpu-info.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun unsigned long PCIBIOS_MIN_IO;
21*4882a593Smuzhiyun EXPORT_SYMBOL(PCIBIOS_MIN_IO);
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun unsigned long PCIBIOS_MIN_MEM;
24*4882a593Smuzhiyun EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
25*4882a593Smuzhiyun 
pcibios_set_cache_line_size(void)26*4882a593Smuzhiyun static int __init pcibios_set_cache_line_size(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	unsigned int lsize;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	/*
31*4882a593Smuzhiyun 	 * Set PCI cacheline size to that of the highest level in the
32*4882a593Smuzhiyun 	 * cache hierarchy.
33*4882a593Smuzhiyun 	 */
34*4882a593Smuzhiyun 	lsize = cpu_dcache_line_size();
35*4882a593Smuzhiyun 	lsize = cpu_scache_line_size() ? : lsize;
36*4882a593Smuzhiyun 	lsize = cpu_tcache_line_size() ? : lsize;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	BUG_ON(!lsize);
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	pci_dfl_cache_line_size = lsize >> 2;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
43*4882a593Smuzhiyun 	return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun arch_initcall(pcibios_set_cache_line_size);
46*4882a593Smuzhiyun 
pci_resource_to_user(const struct pci_dev * dev,int bar,const struct resource * rsrc,resource_size_t * start,resource_size_t * end)47*4882a593Smuzhiyun void pci_resource_to_user(const struct pci_dev *dev, int bar,
48*4882a593Smuzhiyun 			  const struct resource *rsrc, resource_size_t *start,
49*4882a593Smuzhiyun 			  resource_size_t *end)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	phys_addr_t size = resource_size(rsrc);
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	*start = fixup_bigphys_addr(rsrc->start, size);
54*4882a593Smuzhiyun 	*end = rsrc->start + size - 1;
55*4882a593Smuzhiyun }
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