1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
3*4882a593Smuzhiyun * and RBTX49xx patch from CELF patch archive.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2001, 2003-2005 MontaVista Software Inc.
6*4882a593Smuzhiyun * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7*4882a593Smuzhiyun * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
10*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
11*4882a593Smuzhiyun * for more details.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <asm/txx9/generic.h>
18*4882a593Smuzhiyun #include <asm/txx9/tx4939.h>
19*4882a593Smuzhiyun
tx4939_report_pciclk(void)20*4882a593Smuzhiyun int __init tx4939_report_pciclk(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun int pciclk = 0;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun pr_info("PCIC --%s PCICLK:",
25*4882a593Smuzhiyun (__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
26*4882a593Smuzhiyun " PCI66" : "");
27*4882a593Smuzhiyun if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
28*4882a593Smuzhiyun pciclk = txx9_master_clock * 20 / 6;
29*4882a593Smuzhiyun if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
30*4882a593Smuzhiyun pciclk /= 2;
31*4882a593Smuzhiyun pr_cont("Internal(%u.%uMHz)",
32*4882a593Smuzhiyun (pciclk + 50000) / 1000000,
33*4882a593Smuzhiyun ((pciclk + 50000) / 100000) % 10);
34*4882a593Smuzhiyun } else {
35*4882a593Smuzhiyun pr_cont("External");
36*4882a593Smuzhiyun pciclk = -1;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun pr_cont("\n");
39*4882a593Smuzhiyun return pciclk;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
tx4939_report_pci1clk(void)42*4882a593Smuzhiyun void __init tx4939_report_pci1clk(void)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun unsigned int pciclk = txx9_master_clock * 20 / 6;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
47*4882a593Smuzhiyun (pciclk + 50000) / 1000000,
48*4882a593Smuzhiyun ((pciclk + 50000) / 100000) % 10);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
tx4939_pcic1_map_irq(const struct pci_dev * dev,u8 slot)51*4882a593Smuzhiyun int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
54*4882a593Smuzhiyun switch (slot) {
55*4882a593Smuzhiyun case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
56*4882a593Smuzhiyun if (__raw_readq(&tx4939_ccfgptr->pcfg) &
57*4882a593Smuzhiyun TX4939_PCFG_ET0MODE)
58*4882a593Smuzhiyun return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
59*4882a593Smuzhiyun break;
60*4882a593Smuzhiyun case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
61*4882a593Smuzhiyun if (__raw_readq(&tx4939_ccfgptr->pcfg) &
62*4882a593Smuzhiyun TX4939_PCFG_ET1MODE)
63*4882a593Smuzhiyun return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
64*4882a593Smuzhiyun break;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun return -1;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
tx4939_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)71*4882a593Smuzhiyun int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun int irq = tx4939_pcic1_map_irq(dev, slot);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (irq >= 0)
76*4882a593Smuzhiyun return irq;
77*4882a593Smuzhiyun irq = pin;
78*4882a593Smuzhiyun /* IRQ rotation */
79*4882a593Smuzhiyun irq--; /* 0-3 */
80*4882a593Smuzhiyun irq = (irq + 33 - slot) % 4;
81*4882a593Smuzhiyun irq++; /* 1-4 */
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun switch (irq) {
84*4882a593Smuzhiyun case 1:
85*4882a593Smuzhiyun irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
86*4882a593Smuzhiyun break;
87*4882a593Smuzhiyun case 2:
88*4882a593Smuzhiyun irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
89*4882a593Smuzhiyun break;
90*4882a593Smuzhiyun case 3:
91*4882a593Smuzhiyun irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
92*4882a593Smuzhiyun break;
93*4882a593Smuzhiyun case 4:
94*4882a593Smuzhiyun irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
95*4882a593Smuzhiyun break;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun return irq;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
tx4939_setup_pcierr_irq(void)100*4882a593Smuzhiyun void __init tx4939_setup_pcierr_irq(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
103*4882a593Smuzhiyun tx4927_pcierr_interrupt,
104*4882a593Smuzhiyun 0, "PCI error",
105*4882a593Smuzhiyun (void *)TX4939_PCIC_REG))
106*4882a593Smuzhiyun pr_warn("Failed to request irq for PCIERR\n");
107*4882a593Smuzhiyun }
108