1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SNI specific PCI support for RM200/RM300.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (C) 1997 - 2000, 2003 Ralf Baechle <ralf@linux-mips.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun #include <asm/sni.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun * It seems that on the RM200 only lower 3 bits of the 5 bit PCI device
17*4882a593Smuzhiyun * address are decoded. We therefore manually have to reject attempts at
18*4882a593Smuzhiyun * reading outside this range. Being on the paranoid side we only do this
19*4882a593Smuzhiyun * test for bus 0 and hope forwarding and decoding work properly for any
20*4882a593Smuzhiyun * subordinated busses.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * ASIC PCI only supports type 1 config cycles.
23*4882a593Smuzhiyun */
set_config_address(unsigned int busno,unsigned int devfn,int reg)24*4882a593Smuzhiyun static int set_config_address(unsigned int busno, unsigned int devfn, int reg)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun if ((devfn > 255) || (reg > 255))
27*4882a593Smuzhiyun return PCIBIOS_BAD_REGISTER_NUMBER;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (busno == 0 && devfn >= PCI_DEVFN(8, 0))
30*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun *(volatile u32 *)PCIMT_CONFIG_ADDRESS =
33*4882a593Smuzhiyun ((busno & 0xff) << 16) |
34*4882a593Smuzhiyun ((devfn & 0xff) << 8) |
35*4882a593Smuzhiyun (reg & 0xfc);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
pcimt_read(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 * val)40*4882a593Smuzhiyun static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg,
41*4882a593Smuzhiyun int size, u32 * val)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun int res;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if ((res = set_config_address(bus->number, devfn, reg)))
46*4882a593Smuzhiyun return res;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun switch (size) {
49*4882a593Smuzhiyun case 1:
50*4882a593Smuzhiyun *val = inb(PCIMT_CONFIG_DATA + (reg & 3));
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun case 2:
53*4882a593Smuzhiyun *val = inw(PCIMT_CONFIG_DATA + (reg & 2));
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case 4:
56*4882a593Smuzhiyun *val = inl(PCIMT_CONFIG_DATA);
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
pcimt_write(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 val)63*4882a593Smuzhiyun static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
64*4882a593Smuzhiyun int size, u32 val)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun int res;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if ((res = set_config_address(bus->number, devfn, reg)))
69*4882a593Smuzhiyun return res;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun switch (size) {
72*4882a593Smuzhiyun case 1:
73*4882a593Smuzhiyun outb(val, PCIMT_CONFIG_DATA + (reg & 3));
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun case 2:
76*4882a593Smuzhiyun outw(val, PCIMT_CONFIG_DATA + (reg & 2));
77*4882a593Smuzhiyun break;
78*4882a593Smuzhiyun case 4:
79*4882a593Smuzhiyun outl(val, PCIMT_CONFIG_DATA);
80*4882a593Smuzhiyun break;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun struct pci_ops sni_pcimt_ops = {
87*4882a593Smuzhiyun .read = pcimt_read,
88*4882a593Smuzhiyun .write = pcimt_write,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
pcit_set_config_address(unsigned int busno,unsigned int devfn,int reg)91*4882a593Smuzhiyun static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int reg)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun if ((devfn > 255) || (reg > 255) || (busno > 255))
94*4882a593Smuzhiyun return PCIBIOS_BAD_REGISTER_NUMBER;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8);
97*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
pcit_read(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 * val)100*4882a593Smuzhiyun static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg,
101*4882a593Smuzhiyun int size, u32 * val)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun int res;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun * on bus 0 we need to check, whether there is a device answering
107*4882a593Smuzhiyun * for the devfn by doing a config write and checking the result. If
108*4882a593Smuzhiyun * we don't do it, we will get a data bus error
109*4882a593Smuzhiyun */
110*4882a593Smuzhiyun if (bus->number == 0) {
111*4882a593Smuzhiyun pcit_set_config_address(0, 0, 0x68);
112*4882a593Smuzhiyun outl(inl(0xcfc) | 0xc0000000, 0xcfc);
113*4882a593Smuzhiyun if ((res = pcit_set_config_address(0, devfn, 0)))
114*4882a593Smuzhiyun return res;
115*4882a593Smuzhiyun outl(0xffffffff, 0xcfc);
116*4882a593Smuzhiyun pcit_set_config_address(0, 0, 0x68);
117*4882a593Smuzhiyun if (inl(0xcfc) & 0x100000)
118*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun if ((res = pcit_set_config_address(bus->number, devfn, reg)))
121*4882a593Smuzhiyun return res;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun switch (size) {
124*4882a593Smuzhiyun case 1:
125*4882a593Smuzhiyun *val = inb(PCIMT_CONFIG_DATA + (reg & 3));
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun case 2:
128*4882a593Smuzhiyun *val = inw(PCIMT_CONFIG_DATA + (reg & 2));
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun case 4:
131*4882a593Smuzhiyun *val = inl(PCIMT_CONFIG_DATA);
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
pcit_write(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 val)137*4882a593Smuzhiyun static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg,
138*4882a593Smuzhiyun int size, u32 val)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun int res;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if ((res = pcit_set_config_address(bus->number, devfn, reg)))
143*4882a593Smuzhiyun return res;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun switch (size) {
146*4882a593Smuzhiyun case 1:
147*4882a593Smuzhiyun outb(val, PCIMT_CONFIG_DATA + (reg & 3));
148*4882a593Smuzhiyun break;
149*4882a593Smuzhiyun case 2:
150*4882a593Smuzhiyun outw(val, PCIMT_CONFIG_DATA + (reg & 2));
151*4882a593Smuzhiyun break;
152*4882a593Smuzhiyun case 4:
153*4882a593Smuzhiyun outl(val, PCIMT_CONFIG_DATA);
154*4882a593Smuzhiyun break;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun struct pci_ops sni_pcit_ops = {
162*4882a593Smuzhiyun .read = pcit_read,
163*4882a593Smuzhiyun .write = pcit_write,
164*4882a593Smuzhiyun };
165