1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
4*4882a593Smuzhiyun * All rights reserved.
5*4882a593Smuzhiyun * Authors: Carsten Langgaard <carstenl@mips.com>
6*4882a593Smuzhiyun * Maciej W. Rozycki <macro@mips.com>
7*4882a593Smuzhiyun * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * MIPS boards specific PCI support.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/pci.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <asm/mips-boards/msc01_pci.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define PCI_ACCESS_READ 0
18*4882a593Smuzhiyun #define PCI_ACCESS_WRITE 1
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * PCI configuration cycle AD bus definition
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun /* Type 0 */
24*4882a593Smuzhiyun #define PCI_CFG_TYPE0_REG_SHF 0
25*4882a593Smuzhiyun #define PCI_CFG_TYPE0_FUNC_SHF 8
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Type 1 */
28*4882a593Smuzhiyun #define PCI_CFG_TYPE1_REG_SHF 0
29*4882a593Smuzhiyun #define PCI_CFG_TYPE1_FUNC_SHF 8
30*4882a593Smuzhiyun #define PCI_CFG_TYPE1_DEV_SHF 11
31*4882a593Smuzhiyun #define PCI_CFG_TYPE1_BUS_SHF 16
32*4882a593Smuzhiyun
msc_pcibios_config_access(unsigned char access_type,struct pci_bus * bus,unsigned int devfn,int where,u32 * data)33*4882a593Smuzhiyun static int msc_pcibios_config_access(unsigned char access_type,
34*4882a593Smuzhiyun struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun unsigned char busnum = bus->number;
37*4882a593Smuzhiyun u32 intr;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Clear status register bits. */
40*4882a593Smuzhiyun MSC_WRITE(MSC01_PCI_INTSTAT,
41*4882a593Smuzhiyun (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun MSC_WRITE(MSC01_PCI_CFGADDR,
44*4882a593Smuzhiyun ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
45*4882a593Smuzhiyun (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
46*4882a593Smuzhiyun (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
47*4882a593Smuzhiyun ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Perform access */
50*4882a593Smuzhiyun if (access_type == PCI_ACCESS_WRITE)
51*4882a593Smuzhiyun MSC_WRITE(MSC01_PCI_CFGDATA, *data);
52*4882a593Smuzhiyun else
53*4882a593Smuzhiyun MSC_READ(MSC01_PCI_CFGDATA, *data);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Detect Master/Target abort */
56*4882a593Smuzhiyun MSC_READ(MSC01_PCI_INTSTAT, intr);
57*4882a593Smuzhiyun if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
58*4882a593Smuzhiyun /* Error occurred */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Clear bits */
61*4882a593Smuzhiyun MSC_WRITE(MSC01_PCI_INTSTAT,
62*4882a593Smuzhiyun (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return -1;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * We can't address 8 and 16 bit words directly. Instead we have to
73*4882a593Smuzhiyun * read/write a 32bit word and mask/modify the data we actually want.
74*4882a593Smuzhiyun */
msc_pcibios_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)75*4882a593Smuzhiyun static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
76*4882a593Smuzhiyun int where, int size, u32 * val)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun u32 data = 0;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if ((size == 2) && (where & 1))
81*4882a593Smuzhiyun return PCIBIOS_BAD_REGISTER_NUMBER;
82*4882a593Smuzhiyun else if ((size == 4) && (where & 3))
83*4882a593Smuzhiyun return PCIBIOS_BAD_REGISTER_NUMBER;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
86*4882a593Smuzhiyun &data))
87*4882a593Smuzhiyun return -1;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (size == 1)
90*4882a593Smuzhiyun *val = (data >> ((where & 3) << 3)) & 0xff;
91*4882a593Smuzhiyun else if (size == 2)
92*4882a593Smuzhiyun *val = (data >> ((where & 3) << 3)) & 0xffff;
93*4882a593Smuzhiyun else
94*4882a593Smuzhiyun *val = data;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
msc_pcibios_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)99*4882a593Smuzhiyun static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
100*4882a593Smuzhiyun int where, int size, u32 val)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun u32 data = 0;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if ((size == 2) && (where & 1))
105*4882a593Smuzhiyun return PCIBIOS_BAD_REGISTER_NUMBER;
106*4882a593Smuzhiyun else if ((size == 4) && (where & 3))
107*4882a593Smuzhiyun return PCIBIOS_BAD_REGISTER_NUMBER;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (size == 4)
110*4882a593Smuzhiyun data = val;
111*4882a593Smuzhiyun else {
112*4882a593Smuzhiyun if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
113*4882a593Smuzhiyun where, &data))
114*4882a593Smuzhiyun return -1;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (size == 1)
117*4882a593Smuzhiyun data = (data & ~(0xff << ((where & 3) << 3))) |
118*4882a593Smuzhiyun (val << ((where & 3) << 3));
119*4882a593Smuzhiyun else if (size == 2)
120*4882a593Smuzhiyun data = (data & ~(0xffff << ((where & 3) << 3))) |
121*4882a593Smuzhiyun (val << ((where & 3) << 3));
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (msc_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
125*4882a593Smuzhiyun &data))
126*4882a593Smuzhiyun return -1;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun struct pci_ops msc_pci_ops = {
132*4882a593Smuzhiyun .read = msc_pcibios_read,
133*4882a593Smuzhiyun .write = msc_pcibios_write
134*4882a593Smuzhiyun };
135