1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2000, 2001 Keith M Wesolowski
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/pci.h>
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun #include <asm/ip32/mace.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #if 0
14*4882a593Smuzhiyun # define DPRINTK(args...) printk(args);
15*4882a593Smuzhiyun #else
16*4882a593Smuzhiyun # define DPRINTK(args...)
17*4882a593Smuzhiyun #endif
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * O2 has up to 5 PCI devices connected into the MACE bridge. The device
21*4882a593Smuzhiyun * map looks like this:
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * 0 aic7xxx 0
24*4882a593Smuzhiyun * 1 aic7xxx 1
25*4882a593Smuzhiyun * 2 expansion slot
26*4882a593Smuzhiyun * 3 N/C
27*4882a593Smuzhiyun * 4 N/C
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
mkaddr(struct pci_bus * bus,unsigned int devfn,unsigned int reg)30*4882a593Smuzhiyun static inline int mkaddr(struct pci_bus *bus, unsigned int devfn,
31*4882a593Smuzhiyun unsigned int reg)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun return ((bus->number & 0xff) << 16) |
34*4882a593Smuzhiyun ((devfn & 0xff) << 8) |
35*4882a593Smuzhiyun (reg & 0xfc);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static int
mace_pci_read_config(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 * val)40*4882a593Smuzhiyun mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
41*4882a593Smuzhiyun int reg, int size, u32 *val)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun u32 control = mace->pci.control;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* disable master aborts interrupts during config read */
46*4882a593Smuzhiyun mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
47*4882a593Smuzhiyun mace->pci.config_addr = mkaddr(bus, devfn, reg);
48*4882a593Smuzhiyun switch (size) {
49*4882a593Smuzhiyun case 1:
50*4882a593Smuzhiyun *val = mace->pci.config_data.b[(reg & 3) ^ 3];
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun case 2:
53*4882a593Smuzhiyun *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case 4:
56*4882a593Smuzhiyun *val = mace->pci.config_data.l;
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun /* ack possible master abort */
60*4882a593Smuzhiyun mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
61*4882a593Smuzhiyun mace->pci.control = control;
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * someone forgot to set the ultra bit for the onboard
64*4882a593Smuzhiyun * scsi chips; we fake it here
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun if (bus->number == 0 && reg == 0x40 && size == 4 &&
67*4882a593Smuzhiyun (devfn == (1 << 3) || devfn == (2 << 3)))
68*4882a593Smuzhiyun *val |= 0x1000;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static int
mace_pci_write_config(struct pci_bus * bus,unsigned int devfn,int reg,int size,u32 val)76*4882a593Smuzhiyun mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
77*4882a593Smuzhiyun int reg, int size, u32 val)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun mace->pci.config_addr = mkaddr(bus, devfn, reg);
80*4882a593Smuzhiyun switch (size) {
81*4882a593Smuzhiyun case 1:
82*4882a593Smuzhiyun mace->pci.config_data.b[(reg & 3) ^ 3] = val;
83*4882a593Smuzhiyun break;
84*4882a593Smuzhiyun case 2:
85*4882a593Smuzhiyun mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
86*4882a593Smuzhiyun break;
87*4882a593Smuzhiyun case 4:
88*4882a593Smuzhiyun mace->pci.config_data.l = val;
89*4882a593Smuzhiyun break;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun struct pci_ops mace_pci_ops = {
98*4882a593Smuzhiyun .read = mace_pci_read_config,
99*4882a593Smuzhiyun .write = mace_pci_write_config,
100*4882a593Smuzhiyun };
101