1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2010 John Crispin <john@phrozen.org>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/types.h>
8*4882a593Smuzhiyun #include <linux/pci.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/mm.h>
12*4882a593Smuzhiyun #include <asm/addrspace.h>
13*4882a593Smuzhiyun #include <linux/vmalloc.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <lantiq_soc.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "pci-lantiq.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define LTQ_PCI_CFG_BUSNUM_SHF 16
20*4882a593Smuzhiyun #define LTQ_PCI_CFG_DEVNUM_SHF 11
21*4882a593Smuzhiyun #define LTQ_PCI_CFG_FUNNUM_SHF 8
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define PCI_ACCESS_READ 0
24*4882a593Smuzhiyun #define PCI_ACCESS_WRITE 1
25*4882a593Smuzhiyun
ltq_pci_config_access(unsigned char access_type,struct pci_bus * bus,unsigned int devfn,unsigned int where,u32 * data)26*4882a593Smuzhiyun static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
27*4882a593Smuzhiyun unsigned int devfn, unsigned int where, u32 *data)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun unsigned long cfg_base;
30*4882a593Smuzhiyun unsigned long flags;
31*4882a593Smuzhiyun u32 temp;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
34*4882a593Smuzhiyun SoC itself */
35*4882a593Smuzhiyun if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
36*4882a593Smuzhiyun || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
37*4882a593Smuzhiyun return 1;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun spin_lock_irqsave(&ebu_lock, flags);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun cfg_base = (unsigned long) ltq_pci_mapped_cfg;
42*4882a593Smuzhiyun cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
43*4882a593Smuzhiyun LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Perform access */
46*4882a593Smuzhiyun if (access_type == PCI_ACCESS_WRITE) {
47*4882a593Smuzhiyun ltq_w32(swab32(*data), ((u32 *)cfg_base));
48*4882a593Smuzhiyun } else {
49*4882a593Smuzhiyun *data = ltq_r32(((u32 *)(cfg_base)));
50*4882a593Smuzhiyun *data = swab32(*data);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun wmb();
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* clean possible Master abort */
55*4882a593Smuzhiyun cfg_base = (unsigned long) ltq_pci_mapped_cfg;
56*4882a593Smuzhiyun cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
57*4882a593Smuzhiyun temp = ltq_r32(((u32 *)(cfg_base)));
58*4882a593Smuzhiyun temp = swab32(temp);
59*4882a593Smuzhiyun cfg_base = (unsigned long) ltq_pci_mapped_cfg;
60*4882a593Smuzhiyun cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
61*4882a593Smuzhiyun ltq_w32(temp, ((u32 *)cfg_base));
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun spin_unlock_irqrestore(&ebu_lock, flags);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
66*4882a593Smuzhiyun return 1;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
ltq_pci_read_config_dword(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)71*4882a593Smuzhiyun int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
72*4882a593Smuzhiyun int where, int size, u32 *val)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun u32 data = 0;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
77*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (size == 1)
80*4882a593Smuzhiyun *val = (data >> ((where & 3) << 3)) & 0xff;
81*4882a593Smuzhiyun else if (size == 2)
82*4882a593Smuzhiyun *val = (data >> ((where & 3) << 3)) & 0xffff;
83*4882a593Smuzhiyun else
84*4882a593Smuzhiyun *val = data;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
ltq_pci_write_config_dword(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)89*4882a593Smuzhiyun int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
90*4882a593Smuzhiyun int where, int size, u32 val)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun u32 data = 0;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (size == 4) {
95*4882a593Smuzhiyun data = val;
96*4882a593Smuzhiyun } else {
97*4882a593Smuzhiyun if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
98*4882a593Smuzhiyun devfn, where, &data))
99*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (size == 1)
102*4882a593Smuzhiyun data = (data & ~(0xff << ((where & 3) << 3))) |
103*4882a593Smuzhiyun (val << ((where & 3) << 3));
104*4882a593Smuzhiyun else if (size == 2)
105*4882a593Smuzhiyun data = (data & ~(0xffff << ((where & 3) << 3))) |
106*4882a593Smuzhiyun (val << ((where & 3) << 3));
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
110*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
113*4882a593Smuzhiyun }
114