1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@linux-mips.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/pci.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/vr41xx/giu.h>
11*4882a593Smuzhiyun #include <asm/vr41xx/tb0226.h>
12*4882a593Smuzhiyun
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)13*4882a593Smuzhiyun int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun int irq = -1;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun switch (slot) {
18*4882a593Smuzhiyun case 12:
19*4882a593Smuzhiyun vr41xx_set_irq_trigger(GD82559_1_PIN,
20*4882a593Smuzhiyun IRQ_TRIGGER_LEVEL,
21*4882a593Smuzhiyun IRQ_SIGNAL_THROUGH);
22*4882a593Smuzhiyun vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW);
23*4882a593Smuzhiyun irq = GD82559_1_IRQ;
24*4882a593Smuzhiyun break;
25*4882a593Smuzhiyun case 13:
26*4882a593Smuzhiyun vr41xx_set_irq_trigger(GD82559_2_PIN,
27*4882a593Smuzhiyun IRQ_TRIGGER_LEVEL,
28*4882a593Smuzhiyun IRQ_SIGNAL_THROUGH);
29*4882a593Smuzhiyun vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW);
30*4882a593Smuzhiyun irq = GD82559_2_IRQ;
31*4882a593Smuzhiyun break;
32*4882a593Smuzhiyun case 14:
33*4882a593Smuzhiyun switch (pin) {
34*4882a593Smuzhiyun case 1:
35*4882a593Smuzhiyun vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
36*4882a593Smuzhiyun IRQ_TRIGGER_LEVEL,
37*4882a593Smuzhiyun IRQ_SIGNAL_THROUGH);
38*4882a593Smuzhiyun vr41xx_set_irq_level(UPD720100_INTA_PIN,
39*4882a593Smuzhiyun IRQ_LEVEL_LOW);
40*4882a593Smuzhiyun irq = UPD720100_INTA_IRQ;
41*4882a593Smuzhiyun break;
42*4882a593Smuzhiyun case 2:
43*4882a593Smuzhiyun vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
44*4882a593Smuzhiyun IRQ_TRIGGER_LEVEL,
45*4882a593Smuzhiyun IRQ_SIGNAL_THROUGH);
46*4882a593Smuzhiyun vr41xx_set_irq_level(UPD720100_INTB_PIN,
47*4882a593Smuzhiyun IRQ_LEVEL_LOW);
48*4882a593Smuzhiyun irq = UPD720100_INTB_IRQ;
49*4882a593Smuzhiyun break;
50*4882a593Smuzhiyun case 3:
51*4882a593Smuzhiyun vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
52*4882a593Smuzhiyun IRQ_TRIGGER_LEVEL,
53*4882a593Smuzhiyun IRQ_SIGNAL_THROUGH);
54*4882a593Smuzhiyun vr41xx_set_irq_level(UPD720100_INTC_PIN,
55*4882a593Smuzhiyun IRQ_LEVEL_LOW);
56*4882a593Smuzhiyun irq = UPD720100_INTC_IRQ;
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun default:
59*4882a593Smuzhiyun break;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun default:
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return irq;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Do platform specific device initialization at pci_enable_device() time */
pcibios_plat_dev_init(struct pci_dev * dev)70*4882a593Smuzhiyun int pcibios_plat_dev_init(struct pci_dev *dev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74