1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2004, 2006 MIPS Technologies, Inc. All rights reserved.
4*4882a593Smuzhiyun * Author: Maciej W. Rozycki <macro@mips.com>
5*4882a593Smuzhiyun * Copyright (C) 2018 Maciej W. Rozycki
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/dma-mapping.h>
9*4882a593Smuzhiyun #include <linux/pci.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun * Set the BCM1250, etc. PCI host bridge's TRDY timeout
13*4882a593Smuzhiyun * to the finite max.
14*4882a593Smuzhiyun */
quirk_sb1250_pci(struct pci_dev * dev)15*4882a593Smuzhiyun static void quirk_sb1250_pci(struct pci_dev *dev)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun pci_write_config_byte(dev, 0x40, 0xff);
18*4882a593Smuzhiyun }
19*4882a593Smuzhiyun DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
20*4882a593Smuzhiyun quirk_sb1250_pci);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * The BCM1250, etc. PCI host bridge does not support DAC on its 32-bit
24*4882a593Smuzhiyun * bus, so we set the bus's DMA limit accordingly. However the HT link
25*4882a593Smuzhiyun * down the artificial PCI-HT bridge supports 40-bit addressing and the
26*4882a593Smuzhiyun * SP1011 HT-PCI bridge downstream supports both DAC and a 64-bit bus
27*4882a593Smuzhiyun * width, so we record the PCI-HT bridge's secondary and subordinate bus
28*4882a593Smuzhiyun * numbers and do not set the limit for devices present in the inclusive
29*4882a593Smuzhiyun * range of those.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun struct sb1250_bus_dma_limit_exclude {
32*4882a593Smuzhiyun bool set;
33*4882a593Smuzhiyun unsigned char start;
34*4882a593Smuzhiyun unsigned char end;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
sb1250_bus_dma_limit(struct pci_dev * dev,void * data)37*4882a593Smuzhiyun static int sb1250_bus_dma_limit(struct pci_dev *dev, void *data)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct sb1250_bus_dma_limit_exclude *exclude = data;
40*4882a593Smuzhiyun bool exclude_this;
41*4882a593Smuzhiyun bool ht_bridge;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun exclude_this = exclude->set && (dev->bus->number >= exclude->start &&
44*4882a593Smuzhiyun dev->bus->number <= exclude->end);
45*4882a593Smuzhiyun ht_bridge = !exclude->set && (dev->vendor == PCI_VENDOR_ID_SIBYTE &&
46*4882a593Smuzhiyun dev->device == PCI_DEVICE_ID_BCM1250_HT);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (exclude_this) {
49*4882a593Smuzhiyun dev_dbg(&dev->dev, "not disabling DAC for device");
50*4882a593Smuzhiyun } else if (ht_bridge) {
51*4882a593Smuzhiyun exclude->start = dev->subordinate->number;
52*4882a593Smuzhiyun exclude->end = pci_bus_max_busnr(dev->subordinate);
53*4882a593Smuzhiyun exclude->set = true;
54*4882a593Smuzhiyun dev_dbg(&dev->dev, "not disabling DAC for [bus %02x-%02x]",
55*4882a593Smuzhiyun exclude->start, exclude->end);
56*4882a593Smuzhiyun } else {
57*4882a593Smuzhiyun dev_dbg(&dev->dev, "disabling DAC for device");
58*4882a593Smuzhiyun dev->dev.bus_dma_limit = DMA_BIT_MASK(32);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
quirk_sb1250_pci_dac(struct pci_dev * dev)64*4882a593Smuzhiyun static void quirk_sb1250_pci_dac(struct pci_dev *dev)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct sb1250_bus_dma_limit_exclude exclude = { .set = false };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun pci_walk_bus(dev->bus, sb1250_bus_dma_limit, &exclude);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
71*4882a593Smuzhiyun quirk_sb1250_pci_dac);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * The BCM1250, etc. PCI/HT bridge reports as a host bridge.
75*4882a593Smuzhiyun */
quirk_sb1250_ht(struct pci_dev * dev)76*4882a593Smuzhiyun static void quirk_sb1250_ht(struct pci_dev *dev)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun dev->class = PCI_CLASS_BRIDGE_PCI << 8;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
81*4882a593Smuzhiyun quirk_sb1250_ht);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
85*4882a593Smuzhiyun */
quirk_sp1011(struct pci_dev * dev)86*4882a593Smuzhiyun static void quirk_sp1011(struct pci_dev *dev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun pci_write_config_byte(dev, 0x64, 0xff);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIPACKETS, PCI_DEVICE_ID_SP1011,
91*4882a593Smuzhiyun quirk_sp1011);
92