xref: /OK3568_Linux_fs/kernel/arch/mips/pci/fixup-ip32.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #include <linux/init.h>
3*4882a593Smuzhiyun #include <linux/kernel.h>
4*4882a593Smuzhiyun #include <linux/pci.h>
5*4882a593Smuzhiyun #include <asm/ip32/ip32_ints.h>
6*4882a593Smuzhiyun /*
7*4882a593Smuzhiyun  * O2 has up to 5 PCI devices connected into the MACE bridge.  The device
8*4882a593Smuzhiyun  * map looks like this:
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * 0  aic7xxx 0
11*4882a593Smuzhiyun  * 1  aic7xxx 1
12*4882a593Smuzhiyun  * 2  expansion slot
13*4882a593Smuzhiyun  * 3  N/C
14*4882a593Smuzhiyun  * 4  N/C
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define SCSI0  MACEPCI_SCSI0_IRQ
18*4882a593Smuzhiyun #define SCSI1  MACEPCI_SCSI1_IRQ
19*4882a593Smuzhiyun #define INTA0  MACEPCI_SLOT0_IRQ
20*4882a593Smuzhiyun #define INTA1  MACEPCI_SLOT1_IRQ
21*4882a593Smuzhiyun #define INTA2  MACEPCI_SLOT2_IRQ
22*4882a593Smuzhiyun #define INTB   MACEPCI_SHARED0_IRQ
23*4882a593Smuzhiyun #define INTC   MACEPCI_SHARED1_IRQ
24*4882a593Smuzhiyun #define INTD   MACEPCI_SHARED2_IRQ
25*4882a593Smuzhiyun static char irq_tab_mace[][5] = {
26*4882a593Smuzhiyun       /* Dummy	INT#A  INT#B  INT#C  INT#D */
27*4882a593Smuzhiyun 	{0,	    0,	   0,	  0,	 0}, /* This is placeholder row - never used */
28*4882a593Smuzhiyun 	{0,	SCSI0, SCSI0, SCSI0, SCSI0},
29*4882a593Smuzhiyun 	{0,	SCSI1, SCSI1, SCSI1, SCSI1},
30*4882a593Smuzhiyun 	{0,	INTA0,	INTB,  INTC,  INTD},
31*4882a593Smuzhiyun 	{0,	INTA1,	INTC,  INTD,  INTB},
32*4882a593Smuzhiyun 	{0,	INTA2,	INTD,  INTB,  INTC},
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun  * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
38*4882a593Smuzhiyun  * the device (1-4 => A-D), tell what irq to use.  Note that we don't
39*4882a593Smuzhiyun  * in theory have slots 4 and 5, and we never normally use the shared
40*4882a593Smuzhiyun  * irqs.  I suppose a device without a pin A will thank us for doing it
41*4882a593Smuzhiyun  * right if there exists such a broken piece of crap.
42*4882a593Smuzhiyun  */
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)43*4882a593Smuzhiyun int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	return irq_tab_mace[slot][pin];
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* Do platform specific device initialization at pci_enable_device() time */
pcibios_plat_dev_init(struct pci_dev * dev)49*4882a593Smuzhiyun int pcibios_plat_dev_init(struct pci_dev *dev)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	return 0;
52*4882a593Smuzhiyun }
53