1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3*4882a593Smuzhiyun * reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This software is available to you under a choice of one of two
6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the NetLogic
9*4882a593Smuzhiyun * license below:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
12*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
13*4882a593Smuzhiyun * are met:
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * 1. Redistributions of source code must retain the above copyright
16*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
17*4882a593Smuzhiyun * 2. Redistributions in binary form must reproduce the above copyright
18*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
19*4882a593Smuzhiyun * the documentation and/or other materials provided with the
20*4882a593Smuzhiyun * distribution.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23*4882a593Smuzhiyun * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25*4882a593Smuzhiyun * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26*4882a593Smuzhiyun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28*4882a593Smuzhiyun * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29*4882a593Smuzhiyun * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30*4882a593Smuzhiyun * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31*4882a593Smuzhiyun * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32*4882a593Smuzhiyun * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include <linux/kernel.h>
36*4882a593Smuzhiyun #include <linux/of_fdt.h>
37*4882a593Smuzhiyun #include <linux/memblock.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #include <asm/idle.h>
40*4882a593Smuzhiyun #include <asm/reboot.h>
41*4882a593Smuzhiyun #include <asm/time.h>
42*4882a593Smuzhiyun #include <asm/bootinfo.h>
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #include <asm/netlogic/haldefs.h>
45*4882a593Smuzhiyun #include <asm/netlogic/common.h>
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #include <asm/netlogic/xlp-hal/iomap.h>
48*4882a593Smuzhiyun #include <asm/netlogic/xlp-hal/xlp.h>
49*4882a593Smuzhiyun #include <asm/netlogic/xlp-hal/sys.h>
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun uint64_t nlm_io_base;
52*4882a593Smuzhiyun struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
53*4882a593Smuzhiyun cpumask_t nlm_cpumask = CPU_MASK_CPU0;
54*4882a593Smuzhiyun unsigned int nlm_threads_per_core;
55*4882a593Smuzhiyun
nlm_linux_exit(void)56*4882a593Smuzhiyun static void nlm_linux_exit(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun uint64_t sysbase = nlm_get_node(0)->sysbase;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (cpu_is_xlp9xx())
61*4882a593Smuzhiyun nlm_write_sys_reg(sysbase, SYS_9XX_CHIP_RESET, 1);
62*4882a593Smuzhiyun else
63*4882a593Smuzhiyun nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
64*4882a593Smuzhiyun for ( ; ; )
65*4882a593Smuzhiyun cpu_wait();
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
nlm_fixup_mem(void)68*4882a593Smuzhiyun static void nlm_fixup_mem(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun const int pref_backup = 512;
71*4882a593Smuzhiyun struct memblock_region *mem;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun for_each_mem_region(mem) {
74*4882a593Smuzhiyun memblock_remove(mem->base + mem->size - pref_backup,
75*4882a593Smuzhiyun pref_backup);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
xlp_init_mem_from_bars(void)79*4882a593Smuzhiyun static void __init xlp_init_mem_from_bars(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun uint64_t map[16];
82*4882a593Smuzhiyun int i, n;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map)); /* -1 : all nodes */
85*4882a593Smuzhiyun for (i = 0; i < n; i += 2) {
86*4882a593Smuzhiyun /* exclude 0x1000_0000-0x2000_0000, u-boot device */
87*4882a593Smuzhiyun if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
88*4882a593Smuzhiyun map[i+1] = 0x10000000;
89*4882a593Smuzhiyun if (map[i] > 0x10000000 && map[i] < 0x20000000)
90*4882a593Smuzhiyun map[i] = 0x20000000;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun memblock_add(map[i], map[i+1] - map[i]);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
plat_mem_setup(void)96*4882a593Smuzhiyun void __init plat_mem_setup(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun #ifdef CONFIG_SMP
99*4882a593Smuzhiyun nlm_wakeup_secondary_cpus();
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* update TLB size after waking up threads */
102*4882a593Smuzhiyun current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun register_smp_ops(&nlm_smp_ops);
105*4882a593Smuzhiyun #endif
106*4882a593Smuzhiyun _machine_restart = (void (*)(char *))nlm_linux_exit;
107*4882a593Smuzhiyun _machine_halt = nlm_linux_exit;
108*4882a593Smuzhiyun pm_power_off = nlm_linux_exit;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* memory and bootargs from DT */
111*4882a593Smuzhiyun xlp_early_init_devtree();
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (memblock_end_of_DRAM() == 0) {
114*4882a593Smuzhiyun pr_info("Using DRAM BARs for memory map.\n");
115*4882a593Smuzhiyun xlp_init_mem_from_bars();
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun /* Calculate and setup wired entries for mapped kernel */
118*4882a593Smuzhiyun nlm_fixup_mem();
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
get_system_type(void)121*4882a593Smuzhiyun const char *get_system_type(void)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun switch (read_c0_prid() & PRID_IMP_MASK) {
124*4882a593Smuzhiyun case PRID_IMP_NETLOGIC_XLP9XX:
125*4882a593Smuzhiyun case PRID_IMP_NETLOGIC_XLP5XX:
126*4882a593Smuzhiyun case PRID_IMP_NETLOGIC_XLP2XX:
127*4882a593Smuzhiyun return "Broadcom XLPII Series";
128*4882a593Smuzhiyun default:
129*4882a593Smuzhiyun return "Netlogic XLP Series";
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
prom_free_prom_memory(void)133*4882a593Smuzhiyun void __init prom_free_prom_memory(void)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun /* Nothing yet */
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
xlp_mmu_init(void)138*4882a593Smuzhiyun void xlp_mmu_init(void)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun u32 conf4;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (cpu_is_xlpii()) {
143*4882a593Smuzhiyun /* XLPII series has extended pagesize in config 4 */
144*4882a593Smuzhiyun conf4 = read_c0_config4() & ~0x1f00u;
145*4882a593Smuzhiyun write_c0_config4(conf4 | ((PAGE_SHIFT - 10) / 2 << 8));
146*4882a593Smuzhiyun } else {
147*4882a593Smuzhiyun /* enable extended TLB and Large Fixed TLB */
148*4882a593Smuzhiyun write_c0_config6(read_c0_config6() | 0x24);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* set page mask of extended Fixed TLB in config7 */
151*4882a593Smuzhiyun write_c0_config7(PM_DEFAULT_MASK >>
152*4882a593Smuzhiyun (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
nlm_percpu_init(int hwcpuid)156*4882a593Smuzhiyun void nlm_percpu_init(int hwcpuid)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
prom_init(void)160*4882a593Smuzhiyun void __init prom_init(void)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun void *reset_vec;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
165*4882a593Smuzhiyun nlm_init_boot_cpu();
166*4882a593Smuzhiyun xlp_mmu_init();
167*4882a593Smuzhiyun nlm_node_init(0);
168*4882a593Smuzhiyun xlp_dt_init((void *)(long)fw_arg0);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* Update reset entry point with CPU init code */
171*4882a593Smuzhiyun reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS);
172*4882a593Smuzhiyun memset(reset_vec, 0, RESET_VEC_SIZE);
173*4882a593Smuzhiyun memcpy(reset_vec, (void *)nlm_reset_entry,
174*4882a593Smuzhiyun (nlm_reset_entry_end - nlm_reset_entry));
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #ifdef CONFIG_SMP
177*4882a593Smuzhiyun cpumask_setall(&nlm_cpumask);
178*4882a593Smuzhiyun #endif
179*4882a593Smuzhiyun }
180