1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2006, 07 MIPS Technologies, Inc.
7*4882a593Smuzhiyun * written by Ralf Baechle (ralf@linux-mips.org)
8*4882a593Smuzhiyun * written by Ralf Baechle <ralf@linux-mips.org>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 2008 Wind River Systems, Inc.
11*4882a593Smuzhiyun * updated by Tiejun Chen <tiejun.chen@windriver.com>
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * 1. Probe driver for the Malta's UART ports:
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * o 2 ports in the SMC SuperIO
16*4882a593Smuzhiyun * o 1 port in the CBUS UART, a discrete 16550 which normally is only used
17*4882a593Smuzhiyun * for bringups.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * We don't use 8250_platform.c on Malta as it would result in the CBUS
20*4882a593Smuzhiyun * UART becoming ttyS0.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * 2. Register RTC-CMOS platform device on Malta.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun #include <linux/init.h>
25*4882a593Smuzhiyun #include <linux/serial_8250.h>
26*4882a593Smuzhiyun #include <linux/irq.h>
27*4882a593Smuzhiyun #include <linux/platform_device.h>
28*4882a593Smuzhiyun #include <asm/mips-boards/maltaint.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define SMC_PORT(base, int) \
31*4882a593Smuzhiyun { \
32*4882a593Smuzhiyun .iobase = base, \
33*4882a593Smuzhiyun .irq = int, \
34*4882a593Smuzhiyun .uartclk = 1843200, \
35*4882a593Smuzhiyun .iotype = UPIO_PORT, \
36*4882a593Smuzhiyun .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
37*4882a593Smuzhiyun .regshift = 0, \
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static struct plat_serial8250_port uart8250_data[] = {
43*4882a593Smuzhiyun SMC_PORT(0x3F8, 4),
44*4882a593Smuzhiyun SMC_PORT(0x2F8, 3),
45*4882a593Smuzhiyun #ifndef CONFIG_MIPS_CMP
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun .mapbase = 0x1f000900, /* The CBUS UART */
48*4882a593Smuzhiyun .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
49*4882a593Smuzhiyun .uartclk = 3686400, /* Twice the usual clk! */
50*4882a593Smuzhiyun .iotype = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) ?
51*4882a593Smuzhiyun UPIO_MEM32BE : UPIO_MEM32,
52*4882a593Smuzhiyun .flags = CBUS_UART_FLAGS,
53*4882a593Smuzhiyun .regshift = 3,
54*4882a593Smuzhiyun },
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun { },
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static struct platform_device malta_uart8250_device = {
60*4882a593Smuzhiyun .name = "serial8250",
61*4882a593Smuzhiyun .id = PLAT8250_DEV_PLATFORM,
62*4882a593Smuzhiyun .dev = {
63*4882a593Smuzhiyun .platform_data = uart8250_data,
64*4882a593Smuzhiyun },
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static struct platform_device *malta_devices[] __initdata = {
68*4882a593Smuzhiyun &malta_uart8250_device,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
malta_add_devices(void)71*4882a593Smuzhiyun static int __init malta_add_devices(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun return platform_add_devices(malta_devices, ARRAY_SIZE(malta_devices));
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun device_initcall(malta_add_devices);
77