1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
4*4882a593Smuzhiyun * derived from r4xx0.c by David S. Miller (davem@davemloft.net).
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <linux/init.h>
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/sched.h>
9*4882a593Smuzhiyun #include <linux/mm.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/mipsregs.h>
12*4882a593Smuzhiyun #include <asm/bcache.h>
13*4882a593Smuzhiyun #include <asm/cacheops.h>
14*4882a593Smuzhiyun #include <asm/page.h>
15*4882a593Smuzhiyun #include <asm/mmu_context.h>
16*4882a593Smuzhiyun #include <asm/r4kcache.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Secondary cache size in bytes, if present. */
19*4882a593Smuzhiyun static unsigned long scache_size;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define SC_LINE 32
22*4882a593Smuzhiyun #define SC_PAGE (128*SC_LINE)
23*4882a593Smuzhiyun
blast_r5000_scache(void)24*4882a593Smuzhiyun static inline void blast_r5000_scache(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun unsigned long start = INDEX_BASE;
27*4882a593Smuzhiyun unsigned long end = start + scache_size;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun while(start < end) {
30*4882a593Smuzhiyun cache_op(R5K_Page_Invalidate_S, start);
31*4882a593Smuzhiyun start += SC_PAGE;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
r5k_dma_cache_inv_sc(unsigned long addr,unsigned long size)35*4882a593Smuzhiyun static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun unsigned long end, a;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Catch bad driver code */
40*4882a593Smuzhiyun BUG_ON(size == 0);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (size >= scache_size) {
43*4882a593Smuzhiyun blast_r5000_scache();
44*4882a593Smuzhiyun return;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* On the R5000 secondary cache we cannot
48*4882a593Smuzhiyun * invalidate less than a page at a time.
49*4882a593Smuzhiyun * The secondary cache is physically indexed, write-through.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun a = addr & ~(SC_PAGE - 1);
52*4882a593Smuzhiyun end = (addr + size - 1) & ~(SC_PAGE - 1);
53*4882a593Smuzhiyun while (a <= end) {
54*4882a593Smuzhiyun cache_op(R5K_Page_Invalidate_S, a);
55*4882a593Smuzhiyun a += SC_PAGE;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
r5k_sc_enable(void)59*4882a593Smuzhiyun static void r5k_sc_enable(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun unsigned long flags;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun local_irq_save(flags);
64*4882a593Smuzhiyun set_c0_config(R5K_CONF_SE);
65*4882a593Smuzhiyun blast_r5000_scache();
66*4882a593Smuzhiyun local_irq_restore(flags);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
r5k_sc_disable(void)69*4882a593Smuzhiyun static void r5k_sc_disable(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun unsigned long flags;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun local_irq_save(flags);
74*4882a593Smuzhiyun blast_r5000_scache();
75*4882a593Smuzhiyun clear_c0_config(R5K_CONF_SE);
76*4882a593Smuzhiyun local_irq_restore(flags);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
r5k_sc_probe(void)79*4882a593Smuzhiyun static inline int __init r5k_sc_probe(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun unsigned long config = read_c0_config();
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (config & CONF_SC)
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n",
89*4882a593Smuzhiyun scache_size >> 10);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 1;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static struct bcache_ops r5k_sc_ops = {
95*4882a593Smuzhiyun .bc_enable = r5k_sc_enable,
96*4882a593Smuzhiyun .bc_disable = r5k_sc_disable,
97*4882a593Smuzhiyun .bc_wback_inv = r5k_dma_cache_inv_sc,
98*4882a593Smuzhiyun .bc_inv = r5k_dma_cache_inv_sc
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
r5k_sc_init(void)101*4882a593Smuzhiyun void r5k_sc_init(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun if (r5k_sc_probe()) {
104*4882a593Smuzhiyun r5k_sc_enable();
105*4882a593Smuzhiyun bcops = &r5k_sc_ops;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun }
108