1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* IEEE754 floating point arithmetic 3*4882a593Smuzhiyun * double precision: common utilities 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * MIPS floating point support 7*4882a593Smuzhiyun * Copyright (C) 1994-2000 Algorithmics Ltd. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "ieee754dp.h" 11*4882a593Smuzhiyun ieee754dp_tlong(union ieee754dp x)12*4882a593Smuzhiyuns64 ieee754dp_tlong(union ieee754dp x) 13*4882a593Smuzhiyun { 14*4882a593Smuzhiyun u64 residue; 15*4882a593Smuzhiyun int round; 16*4882a593Smuzhiyun int sticky; 17*4882a593Smuzhiyun int odd; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun COMPXDP; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ieee754_clearcx(); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun EXPLODEXDP; 24*4882a593Smuzhiyun FLUSHXDP; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun switch (xc) { 27*4882a593Smuzhiyun case IEEE754_CLASS_SNAN: 28*4882a593Smuzhiyun case IEEE754_CLASS_QNAN: 29*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 30*4882a593Smuzhiyun return ieee754di_indef(); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun case IEEE754_CLASS_INF: 33*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 34*4882a593Smuzhiyun return ieee754di_overflow(xs); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun case IEEE754_CLASS_ZERO: 37*4882a593Smuzhiyun return 0; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun case IEEE754_CLASS_DNORM: 40*4882a593Smuzhiyun case IEEE754_CLASS_NORM: 41*4882a593Smuzhiyun break; 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun if (xe >= 63) { 44*4882a593Smuzhiyun /* look for valid corner case */ 45*4882a593Smuzhiyun if (xe == 63 && xs && xm == DP_HIDDEN_BIT) 46*4882a593Smuzhiyun return -0x8000000000000000LL; 47*4882a593Smuzhiyun /* Set invalid. We will only use overflow for floating 48*4882a593Smuzhiyun point overflow */ 49*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 50*4882a593Smuzhiyun return ieee754di_overflow(xs); 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun /* oh gawd */ 53*4882a593Smuzhiyun if (xe > DP_FBITS) { 54*4882a593Smuzhiyun xm <<= xe - DP_FBITS; 55*4882a593Smuzhiyun } else if (xe < DP_FBITS) { 56*4882a593Smuzhiyun if (xe < -1) { 57*4882a593Smuzhiyun residue = xm; 58*4882a593Smuzhiyun round = 0; 59*4882a593Smuzhiyun sticky = residue != 0; 60*4882a593Smuzhiyun xm = 0; 61*4882a593Smuzhiyun } else { 62*4882a593Smuzhiyun /* Shifting a u64 64 times does not work, 63*4882a593Smuzhiyun * so we do it in two steps. Be aware that xe 64*4882a593Smuzhiyun * may be -1 */ 65*4882a593Smuzhiyun residue = xm << (xe + 1); 66*4882a593Smuzhiyun residue <<= 63 - DP_FBITS; 67*4882a593Smuzhiyun round = (residue >> 63) != 0; 68*4882a593Smuzhiyun sticky = (residue << 1) != 0; 69*4882a593Smuzhiyun xm >>= DP_FBITS - xe; 70*4882a593Smuzhiyun } 71*4882a593Smuzhiyun odd = (xm & 0x1) != 0x0; 72*4882a593Smuzhiyun switch (ieee754_csr.rm) { 73*4882a593Smuzhiyun case FPU_CSR_RN: 74*4882a593Smuzhiyun if (round && (sticky || odd)) 75*4882a593Smuzhiyun xm++; 76*4882a593Smuzhiyun break; 77*4882a593Smuzhiyun case FPU_CSR_RZ: 78*4882a593Smuzhiyun break; 79*4882a593Smuzhiyun case FPU_CSR_RU: /* toward +Infinity */ 80*4882a593Smuzhiyun if ((round || sticky) && !xs) 81*4882a593Smuzhiyun xm++; 82*4882a593Smuzhiyun break; 83*4882a593Smuzhiyun case FPU_CSR_RD: /* toward -Infinity */ 84*4882a593Smuzhiyun if ((round || sticky) && xs) 85*4882a593Smuzhiyun xm++; 86*4882a593Smuzhiyun break; 87*4882a593Smuzhiyun } 88*4882a593Smuzhiyun if ((xm >> 63) != 0) { 89*4882a593Smuzhiyun /* This can happen after rounding */ 90*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 91*4882a593Smuzhiyun return ieee754di_overflow(xs); 92*4882a593Smuzhiyun } 93*4882a593Smuzhiyun if (round || sticky) 94*4882a593Smuzhiyun ieee754_setcx(IEEE754_INEXACT); 95*4882a593Smuzhiyun } 96*4882a593Smuzhiyun if (xs) 97*4882a593Smuzhiyun return -xm; 98*4882a593Smuzhiyun else 99*4882a593Smuzhiyun return xm; 100*4882a593Smuzhiyun } 101