1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* IEEE754 floating point arithmetic 3*4882a593Smuzhiyun * double precision: common utilities 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * MIPS floating point support 7*4882a593Smuzhiyun * Copyright (C) 1994-2000 Algorithmics Ltd. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "ieee754dp.h" 11*4882a593Smuzhiyun ieee754dp_tint(union ieee754dp x)12*4882a593Smuzhiyunint ieee754dp_tint(union ieee754dp x) 13*4882a593Smuzhiyun { 14*4882a593Smuzhiyun u64 residue; 15*4882a593Smuzhiyun int round; 16*4882a593Smuzhiyun int sticky; 17*4882a593Smuzhiyun int odd; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun COMPXDP; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ieee754_clearcx(); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun EXPLODEXDP; 24*4882a593Smuzhiyun FLUSHXDP; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun switch (xc) { 27*4882a593Smuzhiyun case IEEE754_CLASS_SNAN: 28*4882a593Smuzhiyun case IEEE754_CLASS_QNAN: 29*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 30*4882a593Smuzhiyun return ieee754si_indef(); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun case IEEE754_CLASS_INF: 33*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 34*4882a593Smuzhiyun return ieee754si_overflow(xs); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun case IEEE754_CLASS_ZERO: 37*4882a593Smuzhiyun return 0; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun case IEEE754_CLASS_DNORM: 40*4882a593Smuzhiyun case IEEE754_CLASS_NORM: 41*4882a593Smuzhiyun break; 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun if (xe > 31) { 44*4882a593Smuzhiyun /* Set invalid. We will only use overflow for floating 45*4882a593Smuzhiyun point overflow */ 46*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 47*4882a593Smuzhiyun return ieee754si_overflow(xs); 48*4882a593Smuzhiyun } 49*4882a593Smuzhiyun /* oh gawd */ 50*4882a593Smuzhiyun if (xe > DP_FBITS) { 51*4882a593Smuzhiyun xm <<= xe - DP_FBITS; 52*4882a593Smuzhiyun } else if (xe < DP_FBITS) { 53*4882a593Smuzhiyun if (xe < -1) { 54*4882a593Smuzhiyun residue = xm; 55*4882a593Smuzhiyun round = 0; 56*4882a593Smuzhiyun sticky = residue != 0; 57*4882a593Smuzhiyun xm = 0; 58*4882a593Smuzhiyun } else { 59*4882a593Smuzhiyun residue = xm << (64 - DP_FBITS + xe); 60*4882a593Smuzhiyun round = (residue >> 63) != 0; 61*4882a593Smuzhiyun sticky = (residue << 1) != 0; 62*4882a593Smuzhiyun xm >>= DP_FBITS - xe; 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun /* Note: At this point upper 32 bits of xm are guaranteed 65*4882a593Smuzhiyun to be zero */ 66*4882a593Smuzhiyun odd = (xm & 0x1) != 0x0; 67*4882a593Smuzhiyun switch (ieee754_csr.rm) { 68*4882a593Smuzhiyun case FPU_CSR_RN: 69*4882a593Smuzhiyun if (round && (sticky || odd)) 70*4882a593Smuzhiyun xm++; 71*4882a593Smuzhiyun break; 72*4882a593Smuzhiyun case FPU_CSR_RZ: 73*4882a593Smuzhiyun break; 74*4882a593Smuzhiyun case FPU_CSR_RU: /* toward +Infinity */ 75*4882a593Smuzhiyun if ((round || sticky) && !xs) 76*4882a593Smuzhiyun xm++; 77*4882a593Smuzhiyun break; 78*4882a593Smuzhiyun case FPU_CSR_RD: /* toward -Infinity */ 79*4882a593Smuzhiyun if ((round || sticky) && xs) 80*4882a593Smuzhiyun xm++; 81*4882a593Smuzhiyun break; 82*4882a593Smuzhiyun } 83*4882a593Smuzhiyun /* look for valid corner case 0x80000000 */ 84*4882a593Smuzhiyun if ((xm >> 31) != 0 && (xs == 0 || xm != 0x80000000)) { 85*4882a593Smuzhiyun /* This can happen after rounding */ 86*4882a593Smuzhiyun ieee754_setcx(IEEE754_INVALID_OPERATION); 87*4882a593Smuzhiyun return ieee754si_overflow(xs); 88*4882a593Smuzhiyun } 89*4882a593Smuzhiyun if (round || sticky) 90*4882a593Smuzhiyun ieee754_setcx(IEEE754_INEXACT); 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun if (xs) 93*4882a593Smuzhiyun return -xm; 94*4882a593Smuzhiyun else 95*4882a593Smuzhiyun return xm; 96*4882a593Smuzhiyun } 97