1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * IEEE754 floating point arithmetic 4*4882a593Smuzhiyun * double precision: CLASS.f 5*4882a593Smuzhiyun * FPR[fd] = class(FPR[fs]) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * MIPS floating point support 8*4882a593Smuzhiyun * Copyright (C) 2015 Imagination Technologies, Ltd. 9*4882a593Smuzhiyun * Author: Markos Chandras <markos.chandras@imgtec.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "ieee754dp.h" 13*4882a593Smuzhiyun ieee754dp_2008class(union ieee754dp x)14*4882a593Smuzhiyunint ieee754dp_2008class(union ieee754dp x) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun COMPXDP; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun EXPLODEXDP; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * 10 bit mask as follows: 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * bit0 = SNAN 24*4882a593Smuzhiyun * bit1 = QNAN 25*4882a593Smuzhiyun * bit2 = -INF 26*4882a593Smuzhiyun * bit3 = -NORM 27*4882a593Smuzhiyun * bit4 = -DNORM 28*4882a593Smuzhiyun * bit5 = -ZERO 29*4882a593Smuzhiyun * bit6 = INF 30*4882a593Smuzhiyun * bit7 = NORM 31*4882a593Smuzhiyun * bit8 = DNORM 32*4882a593Smuzhiyun * bit9 = ZERO 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun switch(xc) { 36*4882a593Smuzhiyun case IEEE754_CLASS_SNAN: 37*4882a593Smuzhiyun return 0x01; 38*4882a593Smuzhiyun case IEEE754_CLASS_QNAN: 39*4882a593Smuzhiyun return 0x02; 40*4882a593Smuzhiyun case IEEE754_CLASS_INF: 41*4882a593Smuzhiyun return 0x04 << (xs ? 0 : 4); 42*4882a593Smuzhiyun case IEEE754_CLASS_NORM: 43*4882a593Smuzhiyun return 0x08 << (xs ? 0 : 4); 44*4882a593Smuzhiyun case IEEE754_CLASS_DNORM: 45*4882a593Smuzhiyun return 0x10 << (xs ? 0 : 4); 46*4882a593Smuzhiyun case IEEE754_CLASS_ZERO: 47*4882a593Smuzhiyun return 0x20 << (xs ? 0 : 4); 48*4882a593Smuzhiyun default: 49*4882a593Smuzhiyun pr_err("Unknown class: %d\n", xc); 50*4882a593Smuzhiyun return 0; 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun } 53