1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __LOONGSON_SMP_H_ 3*4882a593Smuzhiyun #define __LOONGSON_SMP_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* for Loongson-3 smp support */ 6*4882a593Smuzhiyun extern unsigned long long smp_group[4]; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 4 groups(nodes) in maximum in numa case */ 9*4882a593Smuzhiyun #define SMP_CORE_GROUP0_BASE (smp_group[0]) 10*4882a593Smuzhiyun #define SMP_CORE_GROUP1_BASE (smp_group[1]) 11*4882a593Smuzhiyun #define SMP_CORE_GROUP2_BASE (smp_group[2]) 12*4882a593Smuzhiyun #define SMP_CORE_GROUP3_BASE (smp_group[3]) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 4 cores in each group(node) */ 15*4882a593Smuzhiyun #define SMP_CORE0_OFFSET 0x000 16*4882a593Smuzhiyun #define SMP_CORE1_OFFSET 0x100 17*4882a593Smuzhiyun #define SMP_CORE2_OFFSET 0x200 18*4882a593Smuzhiyun #define SMP_CORE3_OFFSET 0x300 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* ipi registers offsets */ 21*4882a593Smuzhiyun #define STATUS0 0x00 22*4882a593Smuzhiyun #define EN0 0x04 23*4882a593Smuzhiyun #define SET0 0x08 24*4882a593Smuzhiyun #define CLEAR0 0x0c 25*4882a593Smuzhiyun #define STATUS1 0x10 26*4882a593Smuzhiyun #define MASK1 0x14 27*4882a593Smuzhiyun #define SET1 0x18 28*4882a593Smuzhiyun #define CLEAR1 0x1c 29*4882a593Smuzhiyun #define BUF 0x20 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif 32