1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /* Board-specific reboot/shutdown routines
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2009 Lemote Inc.
7*4882a593Smuzhiyun * Author: Wu Zhangjin, wuzhangjin@gmail.com
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/bootinfo.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <loongson.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <cs5536/cs5536.h>
19*4882a593Smuzhiyun #include "ec_kb3310b.h"
20*4882a593Smuzhiyun
reset_cpu(void)21*4882a593Smuzhiyun static void reset_cpu(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * reset cpu to full speed, this is needed when enabling cpu frequency
25*4882a593Smuzhiyun * scalling
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun writel(readl(LOONGSON_CHIPCFG) | 0x7, LOONGSON_CHIPCFG);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* reset support for fuloong2f */
31*4882a593Smuzhiyun
fl2f_reboot(void)32*4882a593Smuzhiyun static void fl2f_reboot(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun reset_cpu();
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* send a reset signal to south bridge.
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset
39*4882a593Smuzhiyun * normally with this reset operation and it will not work in PMON, but
40*4882a593Smuzhiyun * you can type halt command and then reboot, seems the hardware reset
41*4882a593Smuzhiyun * logic not work normally.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun u32 hi, lo;
45*4882a593Smuzhiyun _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo);
46*4882a593Smuzhiyun lo |= 0x00000001;
47*4882a593Smuzhiyun _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
fl2f_shutdown(void)51*4882a593Smuzhiyun static void fl2f_shutdown(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun u32 hi, lo, val;
54*4882a593Smuzhiyun int gpio_base;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* get gpio base */
57*4882a593Smuzhiyun _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
58*4882a593Smuzhiyun gpio_base = lo & 0xff00;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* make cs5536 gpio13 output enable */
61*4882a593Smuzhiyun val = inl(gpio_base + GPIOL_OUT_EN);
62*4882a593Smuzhiyun val &= ~(1 << (16 + 13));
63*4882a593Smuzhiyun val |= (1 << 13);
64*4882a593Smuzhiyun outl(val, gpio_base + GPIOL_OUT_EN);
65*4882a593Smuzhiyun mmiowb();
66*4882a593Smuzhiyun /* make cs5536 gpio13 output low level voltage. */
67*4882a593Smuzhiyun val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
68*4882a593Smuzhiyun val |= (1 << (16 + 13));
69*4882a593Smuzhiyun outl(val, gpio_base + GPIOL_OUT_VAL);
70*4882a593Smuzhiyun mmiowb();
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* reset support for yeeloong2f and mengloong2f notebook */
74*4882a593Smuzhiyun
ml2f_reboot(void)75*4882a593Smuzhiyun static void ml2f_reboot(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun reset_cpu();
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* sending an reset signal to EC(embedded controller) */
80*4882a593Smuzhiyun ec_write(REG_RESET, BIT_RESET_ON);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define yl2f89_reboot ml2f_reboot
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* menglong(7inches) laptop has different shutdown logic from 8.9inches */
86*4882a593Smuzhiyun #define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
87*4882a593Smuzhiyun #define EC_SHUTDOWN_IO_PORT_LOW 0xff2e
88*4882a593Smuzhiyun #define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
89*4882a593Smuzhiyun #define REG_SHUTDOWN_HIGH 0xFC
90*4882a593Smuzhiyun #define REG_SHUTDOWN_LOW 0x29
91*4882a593Smuzhiyun #define BIT_SHUTDOWN_ON (1 << 1)
92*4882a593Smuzhiyun
ml2f_shutdown(void)93*4882a593Smuzhiyun static void ml2f_shutdown(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun u8 val;
96*4882a593Smuzhiyun u64 i;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH);
99*4882a593Smuzhiyun outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW);
100*4882a593Smuzhiyun mmiowb();
101*4882a593Smuzhiyun val = inb(EC_SHUTDOWN_IO_PORT_DATA);
102*4882a593Smuzhiyun outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA);
103*4882a593Smuzhiyun mmiowb();
104*4882a593Smuzhiyun /* need enough wait here... how many microseconds needs? */
105*4882a593Smuzhiyun for (i = 0; i < 0x10000; i++)
106*4882a593Smuzhiyun delay();
107*4882a593Smuzhiyun outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA);
108*4882a593Smuzhiyun mmiowb();
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
yl2f89_shutdown(void)111*4882a593Smuzhiyun static void yl2f89_shutdown(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun /* cpu-gpio0 output low */
114*4882a593Smuzhiyun LOONGSON_GPIODATA &= ~0x00000001;
115*4882a593Smuzhiyun /* cpu-gpio0 as output */
116*4882a593Smuzhiyun LOONGSON_GPIOIE &= ~0x00000001;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
mach_prepare_reboot(void)119*4882a593Smuzhiyun void mach_prepare_reboot(void)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun switch (mips_machtype) {
122*4882a593Smuzhiyun case MACH_LEMOTE_FL2F:
123*4882a593Smuzhiyun case MACH_LEMOTE_NAS:
124*4882a593Smuzhiyun case MACH_LEMOTE_LL2F:
125*4882a593Smuzhiyun fl2f_reboot();
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun case MACH_LEMOTE_ML2F7:
128*4882a593Smuzhiyun ml2f_reboot();
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun case MACH_LEMOTE_YL2F89:
131*4882a593Smuzhiyun yl2f89_reboot();
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun default:
134*4882a593Smuzhiyun break;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
mach_prepare_shutdown(void)138*4882a593Smuzhiyun void mach_prepare_shutdown(void)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun switch (mips_machtype) {
141*4882a593Smuzhiyun case MACH_LEMOTE_FL2F:
142*4882a593Smuzhiyun case MACH_LEMOTE_NAS:
143*4882a593Smuzhiyun case MACH_LEMOTE_LL2F:
144*4882a593Smuzhiyun fl2f_shutdown();
145*4882a593Smuzhiyun break;
146*4882a593Smuzhiyun case MACH_LEMOTE_ML2F7:
147*4882a593Smuzhiyun ml2f_shutdown();
148*4882a593Smuzhiyun break;
149*4882a593Smuzhiyun case MACH_LEMOTE_YL2F89:
150*4882a593Smuzhiyun yl2f89_shutdown();
151*4882a593Smuzhiyun break;
152*4882a593Smuzhiyun default:
153*4882a593Smuzhiyun break;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun }
156