1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2007 Lemote Inc.
4*4882a593Smuzhiyun * Author: Fuxin Zhang, zhangfx@lemote.com
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/export.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/irq_cpu.h>
12*4882a593Smuzhiyun #include <asm/i8259.h>
13*4882a593Smuzhiyun #include <asm/mipsregs.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <loongson.h>
16*4882a593Smuzhiyun #include <machine.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
19*4882a593Smuzhiyun #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
20*4882a593Smuzhiyun #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
21*4882a593Smuzhiyun #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define LOONGSON_INT_BIT_INT0 (1 << 11)
24*4882a593Smuzhiyun #define LOONGSON_INT_BIT_INT1 (1 << 12)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * The generic i8259_irq() make the kernel hang on booting. Since we cannot
28*4882a593Smuzhiyun * get the irq via the IRR directly, we access the ISR instead.
29*4882a593Smuzhiyun */
mach_i8259_irq(void)30*4882a593Smuzhiyun int mach_i8259_irq(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun int irq, isr;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun irq = -1;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
37*4882a593Smuzhiyun raw_spin_lock(&i8259A_lock);
38*4882a593Smuzhiyun isr = inb(PIC_MASTER_CMD) &
39*4882a593Smuzhiyun ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
40*4882a593Smuzhiyun if (!isr)
41*4882a593Smuzhiyun isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
42*4882a593Smuzhiyun irq = ffs(isr) - 1;
43*4882a593Smuzhiyun if (unlikely(irq == 7)) {
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * This may be a spurious interrupt.
46*4882a593Smuzhiyun *
47*4882a593Smuzhiyun * Read the interrupt status register (ISR). If the most
48*4882a593Smuzhiyun * significant bit is not set then there is no valid
49*4882a593Smuzhiyun * interrupt.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun outb(0x0B, PIC_MASTER_ISR); /* ISR register */
52*4882a593Smuzhiyun if (~inb(PIC_MASTER_ISR) & 0x80)
53*4882a593Smuzhiyun irq = -1;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun raw_spin_unlock(&i8259A_lock);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return irq;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun EXPORT_SYMBOL(mach_i8259_irq);
61*4882a593Smuzhiyun
i8259_irqdispatch(void)62*4882a593Smuzhiyun static void i8259_irqdispatch(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun int irq;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun irq = mach_i8259_irq();
67*4882a593Smuzhiyun if (irq >= 0)
68*4882a593Smuzhiyun do_IRQ(irq);
69*4882a593Smuzhiyun else
70*4882a593Smuzhiyun spurious_interrupt();
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
mach_irq_dispatch(unsigned int pending)73*4882a593Smuzhiyun void mach_irq_dispatch(unsigned int pending)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun if (pending & CAUSEF_IP7)
76*4882a593Smuzhiyun do_IRQ(LOONGSON_TIMER_IRQ);
77*4882a593Smuzhiyun else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */
78*4882a593Smuzhiyun do_perfcnt_IRQ();
79*4882a593Smuzhiyun bonito_irqdispatch();
80*4882a593Smuzhiyun } else if (pending & CAUSEF_IP3) /* CPU UART */
81*4882a593Smuzhiyun do_IRQ(LOONGSON_UART_IRQ);
82*4882a593Smuzhiyun else if (pending & CAUSEF_IP2) /* South Bridge */
83*4882a593Smuzhiyun i8259_irqdispatch();
84*4882a593Smuzhiyun else
85*4882a593Smuzhiyun spurious_interrupt();
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
ip6_action(int cpl,void * dev_id)88*4882a593Smuzhiyun static irqreturn_t ip6_action(int cpl, void *dev_id)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun return IRQ_HANDLED;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
mach_init_irq(void)93*4882a593Smuzhiyun void __init mach_init_irq(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun /* init all controller
96*4882a593Smuzhiyun * 0-15 ------> i8259 interrupt
97*4882a593Smuzhiyun * 16-23 ------> mips cpu interrupt
98*4882a593Smuzhiyun * 32-63 ------> bonito irq
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* setup cs5536 as high level trigger */
102*4882a593Smuzhiyun LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
103*4882a593Smuzhiyun LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Sets the first-level interrupt dispatcher. */
106*4882a593Smuzhiyun mips_cpu_irq_init();
107*4882a593Smuzhiyun init_i8259_irqs();
108*4882a593Smuzhiyun bonito_irq_init();
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* setup north bridge irq (bonito) */
111*4882a593Smuzhiyun if (request_irq(LOONGSON_NORTH_BRIDGE_IRQ, ip6_action,
112*4882a593Smuzhiyun IRQF_SHARED | IRQF_NO_THREAD, "cascade", ip6_action))
113*4882a593Smuzhiyun pr_err("Failed to register north bridge cascade interrupt\n");
114*4882a593Smuzhiyun /* setup source bridge irq (i8259) */
115*4882a593Smuzhiyun if (request_irq(LOONGSON_SOUTH_BRIDGE_IRQ, no_action,
116*4882a593Smuzhiyun IRQF_NO_THREAD | IRQF_NO_SUSPEND, "cascade", NULL))
117*4882a593Smuzhiyun pr_err("Failed to register south bridge cascade interrupt\n");
118*4882a593Smuzhiyun }
119