1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2006 - 2008 Lemote Inc. & Institute of Computing Technology
3*4882a593Smuzhiyun * Author: Yanhua, yanh@lemote.com
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
6*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
7*4882a593Smuzhiyun * for more details.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/cpufreq.h>
10*4882a593Smuzhiyun #include <linux/errno.h>
11*4882a593Smuzhiyun #include <linux/export.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/mach-loongson2ef/loongson.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun enum {
16*4882a593Smuzhiyun DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
17*4882a593Smuzhiyun DC_87PT, DC_DISABLE, DC_RESV
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct cpufreq_frequency_table loongson2_clockmod_table[] = {
21*4882a593Smuzhiyun {0, DC_RESV, CPUFREQ_ENTRY_INVALID},
22*4882a593Smuzhiyun {0, DC_ZERO, CPUFREQ_ENTRY_INVALID},
23*4882a593Smuzhiyun {0, DC_25PT, 0},
24*4882a593Smuzhiyun {0, DC_37PT, 0},
25*4882a593Smuzhiyun {0, DC_50PT, 0},
26*4882a593Smuzhiyun {0, DC_62PT, 0},
27*4882a593Smuzhiyun {0, DC_75PT, 0},
28*4882a593Smuzhiyun {0, DC_87PT, 0},
29*4882a593Smuzhiyun {0, DC_DISABLE, 0},
30*4882a593Smuzhiyun {0, DC_RESV, CPUFREQ_TABLE_END},
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
33*4882a593Smuzhiyun
loongson2_cpu_set_rate(unsigned long rate_khz)34*4882a593Smuzhiyun int loongson2_cpu_set_rate(unsigned long rate_khz)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct cpufreq_frequency_table *pos;
37*4882a593Smuzhiyun int regval;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
40*4882a593Smuzhiyun if (rate_khz == pos->frequency)
41*4882a593Smuzhiyun break;
42*4882a593Smuzhiyun if (rate_khz != pos->frequency)
43*4882a593Smuzhiyun return -ENOTSUPP;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun regval = readl(LOONGSON_CHIPCFG);
46*4882a593Smuzhiyun regval = (regval & ~0x7) | (pos->driver_data - 1);
47*4882a593Smuzhiyun writel(regval, LOONGSON_CHIPCFG);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(loongson2_cpu_set_rate);
52