1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2010 John Crispin <john@phrozen.org>
5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/export.h>
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <asm/bootinfo.h>
11*4882a593Smuzhiyun #include <asm/time.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <lantiq_soc.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "../prom.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define SOC_DANUBE "Danube"
18*4882a593Smuzhiyun #define SOC_TWINPASS "Twinpass"
19*4882a593Smuzhiyun #define SOC_AMAZON_SE "Amazon_SE"
20*4882a593Smuzhiyun #define SOC_AR9 "AR9"
21*4882a593Smuzhiyun #define SOC_GR9 "GRX200"
22*4882a593Smuzhiyun #define SOC_VR9 "xRX200"
23*4882a593Smuzhiyun #define SOC_VRX220 "xRX220"
24*4882a593Smuzhiyun #define SOC_AR10 "xRX300"
25*4882a593Smuzhiyun #define SOC_GRX390 "xRX330"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define COMP_DANUBE "lantiq,danube"
28*4882a593Smuzhiyun #define COMP_TWINPASS "lantiq,twinpass"
29*4882a593Smuzhiyun #define COMP_AMAZON_SE "lantiq,ase"
30*4882a593Smuzhiyun #define COMP_AR9 "lantiq,ar9"
31*4882a593Smuzhiyun #define COMP_GR9 "lantiq,gr9"
32*4882a593Smuzhiyun #define COMP_VR9 "lantiq,vr9"
33*4882a593Smuzhiyun #define COMP_AR10 "lantiq,ar10"
34*4882a593Smuzhiyun #define COMP_GRX390 "lantiq,grx390"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define PART_SHIFT 12
37*4882a593Smuzhiyun #define PART_MASK 0x0FFFFFFF
38*4882a593Smuzhiyun #define REV_SHIFT 28
39*4882a593Smuzhiyun #define REV_MASK 0xF0000000
40*4882a593Smuzhiyun
ltq_soc_detect(struct ltq_soc_info * i)41*4882a593Smuzhiyun void __init ltq_soc_detect(struct ltq_soc_info *i)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
44*4882a593Smuzhiyun i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
45*4882a593Smuzhiyun sprintf(i->rev_type, "1.%d", i->rev);
46*4882a593Smuzhiyun switch (i->partnum) {
47*4882a593Smuzhiyun case SOC_ID_DANUBE1:
48*4882a593Smuzhiyun case SOC_ID_DANUBE2:
49*4882a593Smuzhiyun i->name = SOC_DANUBE;
50*4882a593Smuzhiyun i->type = SOC_TYPE_DANUBE;
51*4882a593Smuzhiyun i->compatible = COMP_DANUBE;
52*4882a593Smuzhiyun break;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun case SOC_ID_TWINPASS:
55*4882a593Smuzhiyun i->name = SOC_TWINPASS;
56*4882a593Smuzhiyun i->type = SOC_TYPE_DANUBE;
57*4882a593Smuzhiyun i->compatible = COMP_TWINPASS;
58*4882a593Smuzhiyun break;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun case SOC_ID_ARX188:
61*4882a593Smuzhiyun case SOC_ID_ARX168_1:
62*4882a593Smuzhiyun case SOC_ID_ARX168_2:
63*4882a593Smuzhiyun case SOC_ID_ARX182:
64*4882a593Smuzhiyun i->name = SOC_AR9;
65*4882a593Smuzhiyun i->type = SOC_TYPE_AR9;
66*4882a593Smuzhiyun i->compatible = COMP_AR9;
67*4882a593Smuzhiyun break;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun case SOC_ID_GRX188:
70*4882a593Smuzhiyun case SOC_ID_GRX168:
71*4882a593Smuzhiyun i->name = SOC_GR9;
72*4882a593Smuzhiyun i->type = SOC_TYPE_AR9;
73*4882a593Smuzhiyun i->compatible = COMP_GR9;
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun case SOC_ID_AMAZON_SE_1:
77*4882a593Smuzhiyun case SOC_ID_AMAZON_SE_2:
78*4882a593Smuzhiyun #ifdef CONFIG_PCI
79*4882a593Smuzhiyun panic("ase is only supported for non pci kernels");
80*4882a593Smuzhiyun #endif
81*4882a593Smuzhiyun i->name = SOC_AMAZON_SE;
82*4882a593Smuzhiyun i->type = SOC_TYPE_AMAZON_SE;
83*4882a593Smuzhiyun i->compatible = COMP_AMAZON_SE;
84*4882a593Smuzhiyun break;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun case SOC_ID_VRX282:
87*4882a593Smuzhiyun case SOC_ID_VRX268:
88*4882a593Smuzhiyun case SOC_ID_VRX288:
89*4882a593Smuzhiyun i->name = SOC_VR9;
90*4882a593Smuzhiyun i->type = SOC_TYPE_VR9;
91*4882a593Smuzhiyun i->compatible = COMP_VR9;
92*4882a593Smuzhiyun break;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun case SOC_ID_GRX268:
95*4882a593Smuzhiyun case SOC_ID_GRX288:
96*4882a593Smuzhiyun i->name = SOC_GR9;
97*4882a593Smuzhiyun i->type = SOC_TYPE_VR9;
98*4882a593Smuzhiyun i->compatible = COMP_GR9;
99*4882a593Smuzhiyun break;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun case SOC_ID_VRX268_2:
102*4882a593Smuzhiyun case SOC_ID_VRX288_2:
103*4882a593Smuzhiyun i->name = SOC_VR9;
104*4882a593Smuzhiyun i->type = SOC_TYPE_VR9_2;
105*4882a593Smuzhiyun i->compatible = COMP_VR9;
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun case SOC_ID_VRX220:
109*4882a593Smuzhiyun i->name = SOC_VRX220;
110*4882a593Smuzhiyun i->type = SOC_TYPE_VRX220;
111*4882a593Smuzhiyun i->compatible = COMP_VR9;
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun case SOC_ID_GRX282_2:
115*4882a593Smuzhiyun case SOC_ID_GRX288_2:
116*4882a593Smuzhiyun i->name = SOC_GR9;
117*4882a593Smuzhiyun i->type = SOC_TYPE_VR9_2;
118*4882a593Smuzhiyun i->compatible = COMP_GR9;
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun case SOC_ID_ARX362:
122*4882a593Smuzhiyun case SOC_ID_ARX368:
123*4882a593Smuzhiyun case SOC_ID_ARX382:
124*4882a593Smuzhiyun case SOC_ID_ARX388:
125*4882a593Smuzhiyun case SOC_ID_URX388:
126*4882a593Smuzhiyun i->name = SOC_AR10;
127*4882a593Smuzhiyun i->type = SOC_TYPE_AR10;
128*4882a593Smuzhiyun i->compatible = COMP_AR10;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun case SOC_ID_GRX383:
132*4882a593Smuzhiyun case SOC_ID_GRX369:
133*4882a593Smuzhiyun case SOC_ID_GRX387:
134*4882a593Smuzhiyun case SOC_ID_GRX389:
135*4882a593Smuzhiyun i->name = SOC_GRX390;
136*4882a593Smuzhiyun i->type = SOC_TYPE_GRX390;
137*4882a593Smuzhiyun i->compatible = COMP_GRX390;
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun default:
141*4882a593Smuzhiyun unreachable();
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun }
145