1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> 5*4882a593Smuzhiyun * Copyright (C) 2012 John Crispin <john@phrozen.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/init.h> 9*4882a593Smuzhiyun #include <linux/io.h> 10*4882a593Smuzhiyun #include <linux/pm.h> 11*4882a593Smuzhiyun #include <asm/reboot.h> 12*4882a593Smuzhiyun #include <linux/export.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <lantiq_soc.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Dummy implementation. Used to allow platform code to find out what 18*4882a593Smuzhiyun * source was booted from 19*4882a593Smuzhiyun */ ltq_boot_select(void)20*4882a593Smuzhiyununsigned char ltq_boot_select(void) 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun return BS_SPI; 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define BOOT_REG_BASE (KSEG1 | 0x1F200000) 26*4882a593Smuzhiyun #define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) 27*4882a593Smuzhiyun #define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) 28*4882a593Smuzhiyun #define BOOT_PW1 0x4C545100 29*4882a593Smuzhiyun #define BOOT_PW2 0x0051544C 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define WDT_REG_BASE (KSEG1 | 0x1F8803F0) 32*4882a593Smuzhiyun #define WDT_PW1 0x00BE0000 33*4882a593Smuzhiyun #define WDT_PW2 0x00DC0000 34*4882a593Smuzhiyun machine_restart(char * command)35*4882a593Smuzhiyunstatic void machine_restart(char *command) 36*4882a593Smuzhiyun { 37*4882a593Smuzhiyun local_irq_disable(); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* reboot magic */ 40*4882a593Smuzhiyun ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ 41*4882a593Smuzhiyun ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ 42*4882a593Smuzhiyun ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* watchdog magic */ 45*4882a593Smuzhiyun ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); 46*4882a593Smuzhiyun ltq_w32(WDT_PW2 | 47*4882a593Smuzhiyun (0x3 << 26) | /* PWL */ 48*4882a593Smuzhiyun (0x2 << 24) | /* CLKDIV */ 49*4882a593Smuzhiyun (0x1 << 31) | /* enable */ 50*4882a593Smuzhiyun (1), /* reload */ 51*4882a593Smuzhiyun (void *)WDT_REG_BASE); 52*4882a593Smuzhiyun unreachable(); 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun machine_halt(void)55*4882a593Smuzhiyunstatic void machine_halt(void) 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun local_irq_disable(); 58*4882a593Smuzhiyun unreachable(); 59*4882a593Smuzhiyun } 60*4882a593Smuzhiyun machine_power_off(void)61*4882a593Smuzhiyunstatic void machine_power_off(void) 62*4882a593Smuzhiyun { 63*4882a593Smuzhiyun local_irq_disable(); 64*4882a593Smuzhiyun unreachable(); 65*4882a593Smuzhiyun } 66*4882a593Smuzhiyun mips_reboot_setup(void)67*4882a593Smuzhiyunstatic int __init mips_reboot_setup(void) 68*4882a593Smuzhiyun { 69*4882a593Smuzhiyun _machine_restart = machine_restart; 70*4882a593Smuzhiyun _machine_halt = machine_halt; 71*4882a593Smuzhiyun pm_power_off = machine_power_off; 72*4882a593Smuzhiyun return 0; 73*4882a593Smuzhiyun } 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun arch_initcall(mips_reboot_setup); 76