1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * MIPS SIMD Architecture (MSA) context handling code for KVM. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2015 Imagination Technologies Ltd. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include <asm/asm.h> 12*4882a593Smuzhiyun#include <asm/asm-offsets.h> 13*4882a593Smuzhiyun#include <asm/asmmacro.h> 14*4882a593Smuzhiyun#include <asm/regdef.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun .set noreorder 17*4882a593Smuzhiyun .set noat 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunLEAF(__kvm_save_msa) 20*4882a593Smuzhiyun st_d 0, VCPU_FPR0, a0 21*4882a593Smuzhiyun st_d 1, VCPU_FPR1, a0 22*4882a593Smuzhiyun st_d 2, VCPU_FPR2, a0 23*4882a593Smuzhiyun st_d 3, VCPU_FPR3, a0 24*4882a593Smuzhiyun st_d 4, VCPU_FPR4, a0 25*4882a593Smuzhiyun st_d 5, VCPU_FPR5, a0 26*4882a593Smuzhiyun st_d 6, VCPU_FPR6, a0 27*4882a593Smuzhiyun st_d 7, VCPU_FPR7, a0 28*4882a593Smuzhiyun st_d 8, VCPU_FPR8, a0 29*4882a593Smuzhiyun st_d 9, VCPU_FPR9, a0 30*4882a593Smuzhiyun st_d 10, VCPU_FPR10, a0 31*4882a593Smuzhiyun st_d 11, VCPU_FPR11, a0 32*4882a593Smuzhiyun st_d 12, VCPU_FPR12, a0 33*4882a593Smuzhiyun st_d 13, VCPU_FPR13, a0 34*4882a593Smuzhiyun st_d 14, VCPU_FPR14, a0 35*4882a593Smuzhiyun st_d 15, VCPU_FPR15, a0 36*4882a593Smuzhiyun st_d 16, VCPU_FPR16, a0 37*4882a593Smuzhiyun st_d 17, VCPU_FPR17, a0 38*4882a593Smuzhiyun st_d 18, VCPU_FPR18, a0 39*4882a593Smuzhiyun st_d 19, VCPU_FPR19, a0 40*4882a593Smuzhiyun st_d 20, VCPU_FPR20, a0 41*4882a593Smuzhiyun st_d 21, VCPU_FPR21, a0 42*4882a593Smuzhiyun st_d 22, VCPU_FPR22, a0 43*4882a593Smuzhiyun st_d 23, VCPU_FPR23, a0 44*4882a593Smuzhiyun st_d 24, VCPU_FPR24, a0 45*4882a593Smuzhiyun st_d 25, VCPU_FPR25, a0 46*4882a593Smuzhiyun st_d 26, VCPU_FPR26, a0 47*4882a593Smuzhiyun st_d 27, VCPU_FPR27, a0 48*4882a593Smuzhiyun st_d 28, VCPU_FPR28, a0 49*4882a593Smuzhiyun st_d 29, VCPU_FPR29, a0 50*4882a593Smuzhiyun st_d 30, VCPU_FPR30, a0 51*4882a593Smuzhiyun st_d 31, VCPU_FPR31, a0 52*4882a593Smuzhiyun jr ra 53*4882a593Smuzhiyun nop 54*4882a593Smuzhiyun END(__kvm_save_msa) 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunLEAF(__kvm_restore_msa) 57*4882a593Smuzhiyun ld_d 0, VCPU_FPR0, a0 58*4882a593Smuzhiyun ld_d 1, VCPU_FPR1, a0 59*4882a593Smuzhiyun ld_d 2, VCPU_FPR2, a0 60*4882a593Smuzhiyun ld_d 3, VCPU_FPR3, a0 61*4882a593Smuzhiyun ld_d 4, VCPU_FPR4, a0 62*4882a593Smuzhiyun ld_d 5, VCPU_FPR5, a0 63*4882a593Smuzhiyun ld_d 6, VCPU_FPR6, a0 64*4882a593Smuzhiyun ld_d 7, VCPU_FPR7, a0 65*4882a593Smuzhiyun ld_d 8, VCPU_FPR8, a0 66*4882a593Smuzhiyun ld_d 9, VCPU_FPR9, a0 67*4882a593Smuzhiyun ld_d 10, VCPU_FPR10, a0 68*4882a593Smuzhiyun ld_d 11, VCPU_FPR11, a0 69*4882a593Smuzhiyun ld_d 12, VCPU_FPR12, a0 70*4882a593Smuzhiyun ld_d 13, VCPU_FPR13, a0 71*4882a593Smuzhiyun ld_d 14, VCPU_FPR14, a0 72*4882a593Smuzhiyun ld_d 15, VCPU_FPR15, a0 73*4882a593Smuzhiyun ld_d 16, VCPU_FPR16, a0 74*4882a593Smuzhiyun ld_d 17, VCPU_FPR17, a0 75*4882a593Smuzhiyun ld_d 18, VCPU_FPR18, a0 76*4882a593Smuzhiyun ld_d 19, VCPU_FPR19, a0 77*4882a593Smuzhiyun ld_d 20, VCPU_FPR20, a0 78*4882a593Smuzhiyun ld_d 21, VCPU_FPR21, a0 79*4882a593Smuzhiyun ld_d 22, VCPU_FPR22, a0 80*4882a593Smuzhiyun ld_d 23, VCPU_FPR23, a0 81*4882a593Smuzhiyun ld_d 24, VCPU_FPR24, a0 82*4882a593Smuzhiyun ld_d 25, VCPU_FPR25, a0 83*4882a593Smuzhiyun ld_d 26, VCPU_FPR26, a0 84*4882a593Smuzhiyun ld_d 27, VCPU_FPR27, a0 85*4882a593Smuzhiyun ld_d 28, VCPU_FPR28, a0 86*4882a593Smuzhiyun ld_d 29, VCPU_FPR29, a0 87*4882a593Smuzhiyun ld_d 30, VCPU_FPR30, a0 88*4882a593Smuzhiyun ld_d 31, VCPU_FPR31, a0 89*4882a593Smuzhiyun jr ra 90*4882a593Smuzhiyun nop 91*4882a593Smuzhiyun END(__kvm_restore_msa) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun .macro kvm_restore_msa_upper wr, off, base 94*4882a593Smuzhiyun .set push 95*4882a593Smuzhiyun .set noat 96*4882a593Smuzhiyun#ifdef CONFIG_64BIT 97*4882a593Smuzhiyun ld $1, \off(\base) 98*4882a593Smuzhiyun insert_d \wr, 1 99*4882a593Smuzhiyun#elif defined(CONFIG_CPU_LITTLE_ENDIAN) 100*4882a593Smuzhiyun lw $1, \off(\base) 101*4882a593Smuzhiyun insert_w \wr, 2 102*4882a593Smuzhiyun lw $1, (\off+4)(\base) 103*4882a593Smuzhiyun insert_w \wr, 3 104*4882a593Smuzhiyun#else /* CONFIG_CPU_BIG_ENDIAN */ 105*4882a593Smuzhiyun lw $1, (\off+4)(\base) 106*4882a593Smuzhiyun insert_w \wr, 2 107*4882a593Smuzhiyun lw $1, \off(\base) 108*4882a593Smuzhiyun insert_w \wr, 3 109*4882a593Smuzhiyun#endif 110*4882a593Smuzhiyun .set pop 111*4882a593Smuzhiyun .endm 112*4882a593Smuzhiyun 113*4882a593SmuzhiyunLEAF(__kvm_restore_msa_upper) 114*4882a593Smuzhiyun kvm_restore_msa_upper 0, VCPU_FPR0 +8, a0 115*4882a593Smuzhiyun kvm_restore_msa_upper 1, VCPU_FPR1 +8, a0 116*4882a593Smuzhiyun kvm_restore_msa_upper 2, VCPU_FPR2 +8, a0 117*4882a593Smuzhiyun kvm_restore_msa_upper 3, VCPU_FPR3 +8, a0 118*4882a593Smuzhiyun kvm_restore_msa_upper 4, VCPU_FPR4 +8, a0 119*4882a593Smuzhiyun kvm_restore_msa_upper 5, VCPU_FPR5 +8, a0 120*4882a593Smuzhiyun kvm_restore_msa_upper 6, VCPU_FPR6 +8, a0 121*4882a593Smuzhiyun kvm_restore_msa_upper 7, VCPU_FPR7 +8, a0 122*4882a593Smuzhiyun kvm_restore_msa_upper 8, VCPU_FPR8 +8, a0 123*4882a593Smuzhiyun kvm_restore_msa_upper 9, VCPU_FPR9 +8, a0 124*4882a593Smuzhiyun kvm_restore_msa_upper 10, VCPU_FPR10+8, a0 125*4882a593Smuzhiyun kvm_restore_msa_upper 11, VCPU_FPR11+8, a0 126*4882a593Smuzhiyun kvm_restore_msa_upper 12, VCPU_FPR12+8, a0 127*4882a593Smuzhiyun kvm_restore_msa_upper 13, VCPU_FPR13+8, a0 128*4882a593Smuzhiyun kvm_restore_msa_upper 14, VCPU_FPR14+8, a0 129*4882a593Smuzhiyun kvm_restore_msa_upper 15, VCPU_FPR15+8, a0 130*4882a593Smuzhiyun kvm_restore_msa_upper 16, VCPU_FPR16+8, a0 131*4882a593Smuzhiyun kvm_restore_msa_upper 17, VCPU_FPR17+8, a0 132*4882a593Smuzhiyun kvm_restore_msa_upper 18, VCPU_FPR18+8, a0 133*4882a593Smuzhiyun kvm_restore_msa_upper 19, VCPU_FPR19+8, a0 134*4882a593Smuzhiyun kvm_restore_msa_upper 20, VCPU_FPR20+8, a0 135*4882a593Smuzhiyun kvm_restore_msa_upper 21, VCPU_FPR21+8, a0 136*4882a593Smuzhiyun kvm_restore_msa_upper 22, VCPU_FPR22+8, a0 137*4882a593Smuzhiyun kvm_restore_msa_upper 23, VCPU_FPR23+8, a0 138*4882a593Smuzhiyun kvm_restore_msa_upper 24, VCPU_FPR24+8, a0 139*4882a593Smuzhiyun kvm_restore_msa_upper 25, VCPU_FPR25+8, a0 140*4882a593Smuzhiyun kvm_restore_msa_upper 26, VCPU_FPR26+8, a0 141*4882a593Smuzhiyun kvm_restore_msa_upper 27, VCPU_FPR27+8, a0 142*4882a593Smuzhiyun kvm_restore_msa_upper 28, VCPU_FPR28+8, a0 143*4882a593Smuzhiyun kvm_restore_msa_upper 29, VCPU_FPR29+8, a0 144*4882a593Smuzhiyun kvm_restore_msa_upper 30, VCPU_FPR30+8, a0 145*4882a593Smuzhiyun kvm_restore_msa_upper 31, VCPU_FPR31+8, a0 146*4882a593Smuzhiyun jr ra 147*4882a593Smuzhiyun nop 148*4882a593Smuzhiyun END(__kvm_restore_msa_upper) 149*4882a593Smuzhiyun 150*4882a593SmuzhiyunLEAF(__kvm_restore_msacsr) 151*4882a593Smuzhiyun lw t0, VCPU_MSA_CSR(a0) 152*4882a593Smuzhiyun /* 153*4882a593Smuzhiyun * The ctcmsa must stay at this offset in __kvm_restore_msacsr. 154*4882a593Smuzhiyun * See kvm_mips_csr_die_notify() which handles t0 containing a value 155*4882a593Smuzhiyun * which triggers an MSA FP Exception, which must be stepped over and 156*4882a593Smuzhiyun * ignored since the set cause bits must remain there for the guest. 157*4882a593Smuzhiyun */ 158*4882a593Smuzhiyun _ctcmsa MSA_CSR, t0 159*4882a593Smuzhiyun jr ra 160*4882a593Smuzhiyun nop 161*4882a593Smuzhiyun END(__kvm_restore_msacsr) 162