1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * KVM/MIPS: Interrupts 7*4882a593Smuzhiyun * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 8*4882a593Smuzhiyun * Authors: Sanjay Lal <sanjayl@kymasys.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * MIPS Exception Priorities, exceptions (including interrupts) are queued up 13*4882a593Smuzhiyun * for the guest in the order specified by their priorities 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MIPS_EXC_RESET 0 17*4882a593Smuzhiyun #define MIPS_EXC_SRESET 1 18*4882a593Smuzhiyun #define MIPS_EXC_DEBUG_ST 2 19*4882a593Smuzhiyun #define MIPS_EXC_DEBUG 3 20*4882a593Smuzhiyun #define MIPS_EXC_DDB 4 21*4882a593Smuzhiyun #define MIPS_EXC_NMI 5 22*4882a593Smuzhiyun #define MIPS_EXC_MCHK 6 23*4882a593Smuzhiyun #define MIPS_EXC_INT_TIMER 7 24*4882a593Smuzhiyun #define MIPS_EXC_INT_IO_1 8 25*4882a593Smuzhiyun #define MIPS_EXC_INT_IO_2 9 26*4882a593Smuzhiyun #define MIPS_EXC_EXECUTE 10 27*4882a593Smuzhiyun #define MIPS_EXC_INT_IPI_1 11 28*4882a593Smuzhiyun #define MIPS_EXC_INT_IPI_2 12 29*4882a593Smuzhiyun #define MIPS_EXC_MAX 13 30*4882a593Smuzhiyun /* XXXSL More to follow */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define C_TI (_ULCAST_(1) << 30) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #ifdef CONFIG_KVM_MIPS_VZ 35*4882a593Smuzhiyun #define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (1) 36*4882a593Smuzhiyun #define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (1) 37*4882a593Smuzhiyun #else 38*4882a593Smuzhiyun #define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (0) 39*4882a593Smuzhiyun #define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (0) 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun extern u32 *kvm_priority_to_irq; 43*4882a593Smuzhiyun u32 kvm_irq_to_priority(u32 irq); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority); 46*4882a593Smuzhiyun void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority); 47*4882a593Smuzhiyun int kvm_mips_pending_timer(struct kvm_vcpu *vcpu); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu); 50*4882a593Smuzhiyun void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu); 51*4882a593Smuzhiyun void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu, 52*4882a593Smuzhiyun struct kvm_mips_interrupt *irq); 53*4882a593Smuzhiyun void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu, 54*4882a593Smuzhiyun struct kvm_mips_interrupt *irq); 55*4882a593Smuzhiyun int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority, 56*4882a593Smuzhiyun u32 cause); 57*4882a593Smuzhiyun int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority, 58*4882a593Smuzhiyun u32 cause); 59*4882a593Smuzhiyun void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause); 60