1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * GT641xx IRQ routines.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/hardirq.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/irq.h>
10*4882a593Smuzhiyun #include <linux/spinlock.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/gt64120.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
18*4882a593Smuzhiyun
ack_gt641xx_irq(struct irq_data * d)19*4882a593Smuzhiyun static void ack_gt641xx_irq(struct irq_data *d)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun unsigned long flags;
22*4882a593Smuzhiyun u32 cause;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun raw_spin_lock_irqsave(>641xx_irq_lock, flags);
25*4882a593Smuzhiyun cause = GT_READ(GT_INTRCAUSE_OFS);
26*4882a593Smuzhiyun cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
27*4882a593Smuzhiyun GT_WRITE(GT_INTRCAUSE_OFS, cause);
28*4882a593Smuzhiyun raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
mask_gt641xx_irq(struct irq_data * d)31*4882a593Smuzhiyun static void mask_gt641xx_irq(struct irq_data *d)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun unsigned long flags;
34*4882a593Smuzhiyun u32 mask;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun raw_spin_lock_irqsave(>641xx_irq_lock, flags);
37*4882a593Smuzhiyun mask = GT_READ(GT_INTRMASK_OFS);
38*4882a593Smuzhiyun mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
39*4882a593Smuzhiyun GT_WRITE(GT_INTRMASK_OFS, mask);
40*4882a593Smuzhiyun raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
mask_ack_gt641xx_irq(struct irq_data * d)43*4882a593Smuzhiyun static void mask_ack_gt641xx_irq(struct irq_data *d)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun unsigned long flags;
46*4882a593Smuzhiyun u32 cause, mask;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun raw_spin_lock_irqsave(>641xx_irq_lock, flags);
49*4882a593Smuzhiyun mask = GT_READ(GT_INTRMASK_OFS);
50*4882a593Smuzhiyun mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
51*4882a593Smuzhiyun GT_WRITE(GT_INTRMASK_OFS, mask);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun cause = GT_READ(GT_INTRCAUSE_OFS);
54*4882a593Smuzhiyun cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
55*4882a593Smuzhiyun GT_WRITE(GT_INTRCAUSE_OFS, cause);
56*4882a593Smuzhiyun raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
unmask_gt641xx_irq(struct irq_data * d)59*4882a593Smuzhiyun static void unmask_gt641xx_irq(struct irq_data *d)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun unsigned long flags;
62*4882a593Smuzhiyun u32 mask;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun raw_spin_lock_irqsave(>641xx_irq_lock, flags);
65*4882a593Smuzhiyun mask = GT_READ(GT_INTRMASK_OFS);
66*4882a593Smuzhiyun mask |= GT641XX_IRQ_TO_BIT(d->irq);
67*4882a593Smuzhiyun GT_WRITE(GT_INTRMASK_OFS, mask);
68*4882a593Smuzhiyun raw_spin_unlock_irqrestore(>641xx_irq_lock, flags);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static struct irq_chip gt641xx_irq_chip = {
72*4882a593Smuzhiyun .name = "GT641xx",
73*4882a593Smuzhiyun .irq_ack = ack_gt641xx_irq,
74*4882a593Smuzhiyun .irq_mask = mask_gt641xx_irq,
75*4882a593Smuzhiyun .irq_mask_ack = mask_ack_gt641xx_irq,
76*4882a593Smuzhiyun .irq_unmask = unmask_gt641xx_irq,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
gt641xx_irq_dispatch(void)79*4882a593Smuzhiyun void gt641xx_irq_dispatch(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun u32 cause, mask;
82*4882a593Smuzhiyun int i;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun cause = GT_READ(GT_INTRCAUSE_OFS);
85*4882a593Smuzhiyun mask = GT_READ(GT_INTRMASK_OFS);
86*4882a593Smuzhiyun cause &= mask;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * bit0 : logical or of all the interrupt bits.
90*4882a593Smuzhiyun * bit30: logical or of bits[29:26,20:1].
91*4882a593Smuzhiyun * bit31: logical or of bits[25:1].
92*4882a593Smuzhiyun */
93*4882a593Smuzhiyun for (i = 1; i < 30; i++) {
94*4882a593Smuzhiyun if (cause & (1U << i)) {
95*4882a593Smuzhiyun do_IRQ(GT641XX_IRQ_BASE + i);
96*4882a593Smuzhiyun return;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun atomic_inc(&irq_err_count);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
gt641xx_irq_init(void)103*4882a593Smuzhiyun void __init gt641xx_irq_init(void)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun int i;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun GT_WRITE(GT_INTRMASK_OFS, 0);
108*4882a593Smuzhiyun GT_WRITE(GT_INTRCAUSE_OFS, 0);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun * bit0 : logical or of all the interrupt bits.
112*4882a593Smuzhiyun * bit30: logical or of bits[29:26,20:1].
113*4882a593Smuzhiyun * bit31: logical or of bits[25:1].
114*4882a593Smuzhiyun */
115*4882a593Smuzhiyun for (i = 1; i < 30; i++)
116*4882a593Smuzhiyun irq_set_chip_and_handler(GT641XX_IRQ_BASE + i,
117*4882a593Smuzhiyun >641xx_irq_chip, handle_level_irq);
118*4882a593Smuzhiyun }
119