1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * DS1287 clockevent driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/clockchips.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/mc146818rtc.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/time.h>
14*4882a593Smuzhiyun
ds1287_timer_state(void)15*4882a593Smuzhiyun int ds1287_timer_state(void)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
18*4882a593Smuzhiyun }
19*4882a593Smuzhiyun
ds1287_set_base_clock(unsigned int hz)20*4882a593Smuzhiyun int ds1287_set_base_clock(unsigned int hz)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun u8 rate;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun switch (hz) {
25*4882a593Smuzhiyun case 128:
26*4882a593Smuzhiyun rate = 0x9;
27*4882a593Smuzhiyun break;
28*4882a593Smuzhiyun case 256:
29*4882a593Smuzhiyun rate = 0x8;
30*4882a593Smuzhiyun break;
31*4882a593Smuzhiyun case 1024:
32*4882a593Smuzhiyun rate = 0x6;
33*4882a593Smuzhiyun break;
34*4882a593Smuzhiyun default:
35*4882a593Smuzhiyun return -EINVAL;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
ds1287_set_next_event(unsigned long delta,struct clock_event_device * evt)43*4882a593Smuzhiyun static int ds1287_set_next_event(unsigned long delta,
44*4882a593Smuzhiyun struct clock_event_device *evt)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun return -EINVAL;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
ds1287_shutdown(struct clock_event_device * evt)49*4882a593Smuzhiyun static int ds1287_shutdown(struct clock_event_device *evt)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun u8 val;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun spin_lock(&rtc_lock);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun val = CMOS_READ(RTC_REG_B);
56*4882a593Smuzhiyun val &= ~RTC_PIE;
57*4882a593Smuzhiyun CMOS_WRITE(val, RTC_REG_B);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun spin_unlock(&rtc_lock);
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
ds1287_set_periodic(struct clock_event_device * evt)63*4882a593Smuzhiyun static int ds1287_set_periodic(struct clock_event_device *evt)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun u8 val;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun spin_lock(&rtc_lock);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun val = CMOS_READ(RTC_REG_B);
70*4882a593Smuzhiyun val |= RTC_PIE;
71*4882a593Smuzhiyun CMOS_WRITE(val, RTC_REG_B);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun spin_unlock(&rtc_lock);
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
ds1287_event_handler(struct clock_event_device * dev)77*4882a593Smuzhiyun static void ds1287_event_handler(struct clock_event_device *dev)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static struct clock_event_device ds1287_clockevent = {
82*4882a593Smuzhiyun .name = "ds1287",
83*4882a593Smuzhiyun .features = CLOCK_EVT_FEAT_PERIODIC,
84*4882a593Smuzhiyun .set_next_event = ds1287_set_next_event,
85*4882a593Smuzhiyun .set_state_shutdown = ds1287_shutdown,
86*4882a593Smuzhiyun .set_state_periodic = ds1287_set_periodic,
87*4882a593Smuzhiyun .tick_resume = ds1287_shutdown,
88*4882a593Smuzhiyun .event_handler = ds1287_event_handler,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
ds1287_interrupt(int irq,void * dev_id)91*4882a593Smuzhiyun static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct clock_event_device *cd = &ds1287_clockevent;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Ack the RTC interrupt. */
96*4882a593Smuzhiyun CMOS_READ(RTC_REG_C);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun cd->event_handler(cd);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return IRQ_HANDLED;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
ds1287_clockevent_init(int irq)103*4882a593Smuzhiyun int __init ds1287_clockevent_init(int irq)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun unsigned long flags = IRQF_PERCPU | IRQF_TIMER;
106*4882a593Smuzhiyun struct clock_event_device *cd;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun cd = &ds1287_clockevent;
109*4882a593Smuzhiyun cd->rating = 100;
110*4882a593Smuzhiyun cd->irq = irq;
111*4882a593Smuzhiyun clockevent_set_clock(cd, 32768);
112*4882a593Smuzhiyun cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
113*4882a593Smuzhiyun cd->max_delta_ticks = 0x7fffffff;
114*4882a593Smuzhiyun cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
115*4882a593Smuzhiyun cd->min_delta_ticks = 0x300;
116*4882a593Smuzhiyun cd->cpumask = cpumask_of(0);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun clockevents_register_device(&ds1287_clockevent);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return request_irq(irq, ds1287_interrupt, flags, "ds1287", NULL);
121*4882a593Smuzhiyun }
122