xref: /OK3568_Linux_fs/kernel/arch/mips/include/asm/xtalk/xwidget.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun  * License.  See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun  * for more details.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * xwidget.h - generic crosstalk widget header file, derived from IRIX
7*4882a593Smuzhiyun  * <sys/xtalk/xtalkwidget.h>, revision 1.32.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
10*4882a593Smuzhiyun  * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun #ifndef _ASM_XTALK_XWIDGET_H
13*4882a593Smuzhiyun #define _ASM_XTALK_XWIDGET_H
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun #include <asm/xtalk/xtalk.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define WIDGET_ID			0x04
19*4882a593Smuzhiyun #define WIDGET_STATUS			0x0c
20*4882a593Smuzhiyun #define WIDGET_ERR_UPPER_ADDR		0x14
21*4882a593Smuzhiyun #define WIDGET_ERR_LOWER_ADDR		0x1c
22*4882a593Smuzhiyun #define WIDGET_CONTROL			0x24
23*4882a593Smuzhiyun #define WIDGET_REQ_TIMEOUT		0x2c
24*4882a593Smuzhiyun #define WIDGET_INTDEST_UPPER_ADDR	0x34
25*4882a593Smuzhiyun #define WIDGET_INTDEST_LOWER_ADDR	0x3c
26*4882a593Smuzhiyun #define WIDGET_ERR_CMD_WORD		0x44
27*4882a593Smuzhiyun #define WIDGET_LLP_CFG			0x4c
28*4882a593Smuzhiyun #define WIDGET_TFLUSH			0x54
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* WIDGET_ID */
31*4882a593Smuzhiyun #define WIDGET_REV_NUM			0xf0000000
32*4882a593Smuzhiyun #define WIDGET_PART_NUM			0x0ffff000
33*4882a593Smuzhiyun #define WIDGET_MFG_NUM			0x00000ffe
34*4882a593Smuzhiyun #define WIDGET_REV_NUM_SHFT		28
35*4882a593Smuzhiyun #define WIDGET_PART_NUM_SHFT		12
36*4882a593Smuzhiyun #define WIDGET_MFG_NUM_SHFT		1
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
39*4882a593Smuzhiyun #define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
40*4882a593Smuzhiyun #define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* WIDGET_STATUS */
43*4882a593Smuzhiyun #define WIDGET_LLP_REC_CNT		0xff000000
44*4882a593Smuzhiyun #define WIDGET_LLP_TX_CNT		0x00ff0000
45*4882a593Smuzhiyun #define WIDGET_PENDING			0x0000001f
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* WIDGET_ERR_UPPER_ADDR */
48*4882a593Smuzhiyun #define WIDGET_ERR_UPPER_ADDR_ONLY	0x0000ffff
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* WIDGET_CONTROL */
51*4882a593Smuzhiyun #define WIDGET_F_BAD_PKT		0x00010000
52*4882a593Smuzhiyun #define WIDGET_LLP_XBAR_CRD		0x0000f000
53*4882a593Smuzhiyun #define WIDGET_LLP_XBAR_CRD_SHFT	12
54*4882a593Smuzhiyun #define WIDGET_CLR_RLLP_CNT		0x00000800
55*4882a593Smuzhiyun #define WIDGET_CLR_TLLP_CNT		0x00000400
56*4882a593Smuzhiyun #define WIDGET_SYS_END			0x00000200
57*4882a593Smuzhiyun #define WIDGET_MAX_TRANS		0x000001f0
58*4882a593Smuzhiyun #define WIDGET_WIDGET_ID		0x0000000f
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* WIDGET_INTDEST_UPPER_ADDR */
61*4882a593Smuzhiyun #define WIDGET_INT_VECTOR		0xff000000
62*4882a593Smuzhiyun #define WIDGET_INT_VECTOR_SHFT		24
63*4882a593Smuzhiyun #define WIDGET_TARGET_ID		0x000f0000
64*4882a593Smuzhiyun #define WIDGET_TARGET_ID_SHFT		16
65*4882a593Smuzhiyun #define WIDGET_UPP_ADDR			0x0000ffff
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /* WIDGET_ERR_CMD_WORD */
68*4882a593Smuzhiyun #define WIDGET_DIDN			0xf0000000
69*4882a593Smuzhiyun #define WIDGET_SIDN			0x0f000000
70*4882a593Smuzhiyun #define WIDGET_PACTYP			0x00f00000
71*4882a593Smuzhiyun #define WIDGET_TNUM			0x000f8000
72*4882a593Smuzhiyun #define WIDGET_COHERENT			0x00004000
73*4882a593Smuzhiyun #define WIDGET_DS			0x00003000
74*4882a593Smuzhiyun #define WIDGET_GBR			0x00000800
75*4882a593Smuzhiyun #define WIDGET_VBPM			0x00000400
76*4882a593Smuzhiyun #define WIDGET_ERROR			0x00000200
77*4882a593Smuzhiyun #define WIDGET_BARRIER			0x00000100
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /* WIDGET_LLP_CFG */
80*4882a593Smuzhiyun #define WIDGET_LLP_MAXRETRY		0x03ff0000
81*4882a593Smuzhiyun #define WIDGET_LLP_MAXRETRY_SHFT	16
82*4882a593Smuzhiyun #define WIDGET_LLP_NULLTIMEOUT		0x0000fc00
83*4882a593Smuzhiyun #define WIDGET_LLP_NULLTIMEOUT_SHFT	10
84*4882a593Smuzhiyun #define WIDGET_LLP_MAXBURST		0x000003ff
85*4882a593Smuzhiyun #define WIDGET_LLP_MAXBURST_SHFT	0
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* Xtalk Widget Device Mfgr Nums */
88*4882a593Smuzhiyun #define WIDGET_XBOW_MFGR_NUM	0x0      /* IP30 XBow Chip */
89*4882a593Smuzhiyun #define WIDGET_XXBOW_MFGR_NUM	0x0      /* IP35 Xbow + XBridge Chip */
90*4882a593Smuzhiyun #define WIDGET_ODYS_MFGR_NUM	0x023    /* Odyssey / VPro GFX */
91*4882a593Smuzhiyun #define WIDGET_TPU_MFGR_NUM	0x024    /* Tensor Processor Unit */
92*4882a593Smuzhiyun #define WIDGET_XBRDG_MFGR_NUM	0x024    /* IP35 XBridge Chip */
93*4882a593Smuzhiyun #define WIDGET_HEART_MFGR_NUM	0x036    /* IP30 HEART Chip */
94*4882a593Smuzhiyun #define WIDGET_BRIDG_MFGR_NUM	0x036    /* PCI Bridge */
95*4882a593Smuzhiyun #define WIDGET_HUB_MFGR_NUM	0x036    /* IP27 Hub Chip */
96*4882a593Smuzhiyun #define WIDGET_BDRCK_MFGR_NUM	0x036    /* IP35 Bedrock Chip */
97*4882a593Smuzhiyun #define WIDGET_IMPCT_MFGR_NUM	0x2aa    /* HQ4 / Impact GFX */
98*4882a593Smuzhiyun #define WIDGET_KONA_MFGR_NUM	0x2aa    /* InfiniteReality3 / Kona GFX */
99*4882a593Smuzhiyun #define WIDGET_NULL_MFGR_NUM	-1       /* NULL */
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* Xtalk Widget Device Part Nums */
102*4882a593Smuzhiyun #define WIDGET_XBOW_PART_NUM	0x0000
103*4882a593Smuzhiyun #define WIDGET_HEART_PART_NUM	0xc001
104*4882a593Smuzhiyun #define WIDGET_BRIDG_PART_NUM	0xc002
105*4882a593Smuzhiyun #define WIDGET_IMPCT_PART_NUM	0xc003
106*4882a593Smuzhiyun #define WIDGET_ODYS_PART_NUM	0xc013
107*4882a593Smuzhiyun #define WIDGET_HUB_PART_NUM	0xc101
108*4882a593Smuzhiyun #define WIDGET_KONA_PART_NUM	0xc102
109*4882a593Smuzhiyun #define WIDGET_BDRCK_PART_NUM	0xc110
110*4882a593Smuzhiyun #define WIDGET_TPU_PART_NUM	0xc202
111*4882a593Smuzhiyun #define WIDGET_XXBOW_PART_NUM	0xd000
112*4882a593Smuzhiyun #define WIDGET_XBRDG_PART_NUM	0xd002
113*4882a593Smuzhiyun #define WIDGET_NULL_PART_NUM	-1
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* For Xtalk Widget identification */
116*4882a593Smuzhiyun struct widget_ident {
117*4882a593Smuzhiyun 	u32 mfgr;
118*4882a593Smuzhiyun 	u32 part;
119*4882a593Smuzhiyun 	char *name;
120*4882a593Smuzhiyun 	char *revs[16];
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* Known Xtalk Widgets */
124*4882a593Smuzhiyun static const struct widget_ident __initconst widget_idents[] = {
125*4882a593Smuzhiyun 	{
126*4882a593Smuzhiyun 		WIDGET_XBOW_MFGR_NUM,
127*4882a593Smuzhiyun 		WIDGET_XBOW_PART_NUM,
128*4882a593Smuzhiyun 		"xbow",
129*4882a593Smuzhiyun 		{NULL, "1.0", "1.1", "1.2", "1.3", "2.0", NULL},
130*4882a593Smuzhiyun 	},
131*4882a593Smuzhiyun 	{
132*4882a593Smuzhiyun 		WIDGET_HEART_MFGR_NUM,
133*4882a593Smuzhiyun 		WIDGET_HEART_PART_NUM,
134*4882a593Smuzhiyun 		"heart",
135*4882a593Smuzhiyun 		{NULL, "A", "B", "C", "D", "E", "F", NULL},
136*4882a593Smuzhiyun 	},
137*4882a593Smuzhiyun 	{
138*4882a593Smuzhiyun 		WIDGET_BRIDG_MFGR_NUM,
139*4882a593Smuzhiyun 		WIDGET_BRIDG_PART_NUM,
140*4882a593Smuzhiyun 		"bridge",
141*4882a593Smuzhiyun 		{NULL, "A", "B", "C", "D", NULL},
142*4882a593Smuzhiyun 	},
143*4882a593Smuzhiyun 	{
144*4882a593Smuzhiyun 		WIDGET_IMPCT_MFGR_NUM,
145*4882a593Smuzhiyun 		WIDGET_IMPCT_PART_NUM,
146*4882a593Smuzhiyun 		"impact",
147*4882a593Smuzhiyun 		{NULL, "A", "B", NULL},
148*4882a593Smuzhiyun 	},
149*4882a593Smuzhiyun 	{
150*4882a593Smuzhiyun 		WIDGET_ODYS_MFGR_NUM,
151*4882a593Smuzhiyun 		WIDGET_ODYS_PART_NUM,
152*4882a593Smuzhiyun 		"odyssey",
153*4882a593Smuzhiyun 		{NULL, "A", "B", NULL},
154*4882a593Smuzhiyun 	},
155*4882a593Smuzhiyun 	{
156*4882a593Smuzhiyun 		WIDGET_HUB_MFGR_NUM,
157*4882a593Smuzhiyun 		WIDGET_HUB_PART_NUM,
158*4882a593Smuzhiyun 		"hub",
159*4882a593Smuzhiyun 		{NULL, "1.0", "2.0", "2.1", "2.2", "2.3", "2.4", NULL},
160*4882a593Smuzhiyun 	},
161*4882a593Smuzhiyun 	{
162*4882a593Smuzhiyun 		WIDGET_KONA_MFGR_NUM,
163*4882a593Smuzhiyun 		WIDGET_KONA_PART_NUM,
164*4882a593Smuzhiyun 		"kona",
165*4882a593Smuzhiyun 		{NULL},
166*4882a593Smuzhiyun 	},
167*4882a593Smuzhiyun 	{
168*4882a593Smuzhiyun 		WIDGET_BDRCK_MFGR_NUM,
169*4882a593Smuzhiyun 		WIDGET_BDRCK_PART_NUM,
170*4882a593Smuzhiyun 		"bedrock",
171*4882a593Smuzhiyun 		{NULL, "1.0", "1.1", NULL},
172*4882a593Smuzhiyun 	},
173*4882a593Smuzhiyun 	{
174*4882a593Smuzhiyun 		WIDGET_TPU_MFGR_NUM,
175*4882a593Smuzhiyun 		WIDGET_TPU_PART_NUM,
176*4882a593Smuzhiyun 		"tpu",
177*4882a593Smuzhiyun 		{"0", NULL},
178*4882a593Smuzhiyun 	},
179*4882a593Smuzhiyun 	{
180*4882a593Smuzhiyun 		WIDGET_XXBOW_MFGR_NUM,
181*4882a593Smuzhiyun 		WIDGET_XXBOW_PART_NUM,
182*4882a593Smuzhiyun 		"xxbow",
183*4882a593Smuzhiyun 		{NULL, "1.0", "2.0", NULL},
184*4882a593Smuzhiyun 	},
185*4882a593Smuzhiyun 	{
186*4882a593Smuzhiyun 		WIDGET_XBRDG_MFGR_NUM,
187*4882a593Smuzhiyun 		WIDGET_XBRDG_PART_NUM,
188*4882a593Smuzhiyun 		"xbridge",
189*4882a593Smuzhiyun 		{NULL, "A", "B", NULL},
190*4882a593Smuzhiyun 	},
191*4882a593Smuzhiyun 	{
192*4882a593Smuzhiyun 		WIDGET_NULL_MFGR_NUM,
193*4882a593Smuzhiyun 		WIDGET_NULL_PART_NUM,
194*4882a593Smuzhiyun 		NULL,
195*4882a593Smuzhiyun 		{NULL},
196*4882a593Smuzhiyun 	}
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun /*
200*4882a593Smuzhiyun  * according to the crosstalk spec, only 32-bits access to the widget
201*4882a593Smuzhiyun  * configuration registers is allowed.	some widgets may allow 64-bits
202*4882a593Smuzhiyun  * access but software should not depend on it.	 registers beyond the
203*4882a593Smuzhiyun  * widget target flush register are widget dependent thus will not be
204*4882a593Smuzhiyun  * defined here
205*4882a593Smuzhiyun  */
206*4882a593Smuzhiyun #ifndef __ASSEMBLY__
207*4882a593Smuzhiyun typedef u32 widgetreg_t;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun /* widget configuration registers */
210*4882a593Smuzhiyun typedef volatile struct widget_cfg {
211*4882a593Smuzhiyun 	widgetreg_t		w_pad_0;		/* 0x00 */
212*4882a593Smuzhiyun 	widgetreg_t		w_id;			/* 0x04 */
213*4882a593Smuzhiyun 	widgetreg_t		w_pad_1;		/* 0x08 */
214*4882a593Smuzhiyun 	widgetreg_t		w_status;		/* 0x0c */
215*4882a593Smuzhiyun 	widgetreg_t		w_pad_2;		/* 0x10 */
216*4882a593Smuzhiyun 	widgetreg_t		w_err_upper_addr;	/* 0x14 */
217*4882a593Smuzhiyun 	widgetreg_t		w_pad_3;		/* 0x18 */
218*4882a593Smuzhiyun 	widgetreg_t		w_err_lower_addr;	/* 0x1c */
219*4882a593Smuzhiyun 	widgetreg_t		w_pad_4;		/* 0x20 */
220*4882a593Smuzhiyun 	widgetreg_t		w_control;		/* 0x24 */
221*4882a593Smuzhiyun 	widgetreg_t		w_pad_5;		/* 0x28 */
222*4882a593Smuzhiyun 	widgetreg_t		w_req_timeout;		/* 0x2c */
223*4882a593Smuzhiyun 	widgetreg_t		w_pad_6;		/* 0x30 */
224*4882a593Smuzhiyun 	widgetreg_t		w_intdest_upper_addr;	/* 0x34 */
225*4882a593Smuzhiyun 	widgetreg_t		w_pad_7;		/* 0x38 */
226*4882a593Smuzhiyun 	widgetreg_t		w_intdest_lower_addr;	/* 0x3c */
227*4882a593Smuzhiyun 	widgetreg_t		w_pad_8;		/* 0x40 */
228*4882a593Smuzhiyun 	widgetreg_t		w_err_cmd_word;		/* 0x44 */
229*4882a593Smuzhiyun 	widgetreg_t		w_pad_9;		/* 0x48 */
230*4882a593Smuzhiyun 	widgetreg_t		w_llp_cfg;		/* 0x4c */
231*4882a593Smuzhiyun 	widgetreg_t		w_pad_10;		/* 0x50 */
232*4882a593Smuzhiyun 	widgetreg_t		w_tflush;		/* 0x54 */
233*4882a593Smuzhiyun } widget_cfg_t;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun typedef struct {
236*4882a593Smuzhiyun 	unsigned	didn:4;
237*4882a593Smuzhiyun 	unsigned	sidn:4;
238*4882a593Smuzhiyun 	unsigned	pactyp:4;
239*4882a593Smuzhiyun 	unsigned	tnum:5;
240*4882a593Smuzhiyun 	unsigned	ct:1;
241*4882a593Smuzhiyun 	unsigned	ds:2;
242*4882a593Smuzhiyun 	unsigned	gbr:1;
243*4882a593Smuzhiyun 	unsigned	vbpm:1;
244*4882a593Smuzhiyun 	unsigned	error:1;
245*4882a593Smuzhiyun 	unsigned	bo:1;
246*4882a593Smuzhiyun 	unsigned	other:8;
247*4882a593Smuzhiyun } w_err_cmd_word_f;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun typedef union {
250*4882a593Smuzhiyun 	widgetreg_t		r;
251*4882a593Smuzhiyun 	w_err_cmd_word_f	f;
252*4882a593Smuzhiyun } w_err_cmd_word_u;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun typedef struct xwidget_info_s *xwidget_info_t;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun /*
257*4882a593Smuzhiyun  * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
258*4882a593Smuzhiyun  */
259*4882a593Smuzhiyun typedef struct xwidget_hwid_s {
260*4882a593Smuzhiyun 	xwidget_part_num_t	part_num;
261*4882a593Smuzhiyun 	xwidget_rev_num_t	rev_num;
262*4882a593Smuzhiyun 	xwidget_mfg_num_t	mfg_num;
263*4882a593Smuzhiyun } *xwidget_hwid_t;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun /*
267*4882a593Smuzhiyun  * Returns 1 if a driver that handles devices described by hwid1 is able
268*4882a593Smuzhiyun  * to manage a device with hardwareid hwid2.  NOTE: We don't check rev
269*4882a593Smuzhiyun  * numbers at all.
270*4882a593Smuzhiyun  */
271*4882a593Smuzhiyun #define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \
272*4882a593Smuzhiyun 	(((hwid1)->part_num == (hwid2)->part_num) && \
273*4882a593Smuzhiyun 	(((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
274*4882a593Smuzhiyun 	((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
275*4882a593Smuzhiyun 	((hwid1)->mfg_num == (hwid2)->mfg_num)))
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun #endif /* _ASM_XTALK_XWIDGET_H */
280