1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2002, 2004, 2007 by Ralf Baechle 7*4882a593Smuzhiyun * Copyright (C) 2007 Maciej W. Rozycki 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef _ASM_WAR_H 10*4882a593Smuzhiyun #define _ASM_WAR_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Work around certain R4000 CPU errata (as implemented by GCC): 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * - A double-word or a variable shift may give an incorrect result 16*4882a593Smuzhiyun * if executed immediately after starting an integer division: 17*4882a593Smuzhiyun * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", 18*4882a593Smuzhiyun * erratum #28 19*4882a593Smuzhiyun * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum 20*4882a593Smuzhiyun * #19 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * - A double-word or a variable shift may give an incorrect result 23*4882a593Smuzhiyun * if executed while an integer multiplication is in progress: 24*4882a593Smuzhiyun * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", 25*4882a593Smuzhiyun * errata #16 & #28 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * - An integer division may give an incorrect result if started in 28*4882a593Smuzhiyun * a delay slot of a taken branch or a jump: 29*4882a593Smuzhiyun * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", 30*4882a593Smuzhiyun * erratum #52 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #ifdef CONFIG_CPU_R4000_WORKAROUNDS 33*4882a593Smuzhiyun #define R4000_WAR 1 34*4882a593Smuzhiyun #else 35*4882a593Smuzhiyun #define R4000_WAR 0 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Work around certain R4400 CPU errata (as implemented by GCC): 40*4882a593Smuzhiyun * 41*4882a593Smuzhiyun * - A double-word or a variable shift may give an incorrect result 42*4882a593Smuzhiyun * if executed immediately after starting an integer division: 43*4882a593Smuzhiyun * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10 44*4882a593Smuzhiyun * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun #ifdef CONFIG_CPU_R4400_WORKAROUNDS 47*4882a593Smuzhiyun #define R4400_WAR 1 48*4882a593Smuzhiyun #else 49*4882a593Smuzhiyun #define R4400_WAR 0 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * Work around the "daddi" and "daddiu" CPU errata: 54*4882a593Smuzhiyun * 55*4882a593Smuzhiyun * - The `daddi' instruction fails to trap on overflow. 56*4882a593Smuzhiyun * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", 57*4882a593Smuzhiyun * erratum #23 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * - The `daddiu' instruction can produce an incorrect result. 60*4882a593Smuzhiyun * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0", 61*4882a593Smuzhiyun * erratum #41 62*4882a593Smuzhiyun * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum 63*4882a593Smuzhiyun * #15 64*4882a593Smuzhiyun * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7 65*4882a593Smuzhiyun * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun #ifdef CONFIG_CPU_DADDI_WORKAROUNDS 68*4882a593Smuzhiyun #define DADDI_WAR 1 69*4882a593Smuzhiyun #else 70*4882a593Smuzhiyun #define DADDI_WAR 0 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* _ASM_WAR_H */ 74