1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * include/asm-mips/vr41xx/vr41xx.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Include file for NEC VR4100 series.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1999 Michael Klar
8*4882a593Smuzhiyun * Copyright (C) 2001, 2002 Paul Mundt
9*4882a593Smuzhiyun * Copyright (C) 2002 MontaVista Software, Inc.
10*4882a593Smuzhiyun * Copyright (C) 2002 TimeSys Corp.
11*4882a593Smuzhiyun * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #ifndef __NEC_VR41XX_H
14*4882a593Smuzhiyun #define __NEC_VR41XX_H
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * CPU Revision
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun /* VR4122 0x00000c70-0x00000c72 */
22*4882a593Smuzhiyun #define PRID_VR4122_REV1_0 0x00000c70
23*4882a593Smuzhiyun #define PRID_VR4122_REV2_0 0x00000c70
24*4882a593Smuzhiyun #define PRID_VR4122_REV2_1 0x00000c70
25*4882a593Smuzhiyun #define PRID_VR4122_REV3_0 0x00000c71
26*4882a593Smuzhiyun #define PRID_VR4122_REV3_1 0x00000c72
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* VR4181A 0x00000c73-0x00000c7f */
29*4882a593Smuzhiyun #define PRID_VR4181A_REV1_0 0x00000c73
30*4882a593Smuzhiyun #define PRID_VR4181A_REV1_1 0x00000c74
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* VR4131 0x00000c80-0x00000c83 */
33*4882a593Smuzhiyun #define PRID_VR4131_REV1_2 0x00000c80
34*4882a593Smuzhiyun #define PRID_VR4131_REV2_0 0x00000c81
35*4882a593Smuzhiyun #define PRID_VR4131_REV2_1 0x00000c82
36*4882a593Smuzhiyun #define PRID_VR4131_REV2_2 0x00000c83
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* VR4133 0x00000c84- */
39*4882a593Smuzhiyun #define PRID_VR4133 0x00000c84
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * Bus Control Uint
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun extern unsigned long vr41xx_calculate_clock_frequency(void);
45*4882a593Smuzhiyun extern unsigned long vr41xx_get_vtclock_frequency(void);
46*4882a593Smuzhiyun extern unsigned long vr41xx_get_tclock_frequency(void);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * Clock Mask Unit
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun typedef enum {
52*4882a593Smuzhiyun PIU_CLOCK,
53*4882a593Smuzhiyun SIU_CLOCK,
54*4882a593Smuzhiyun AIU_CLOCK,
55*4882a593Smuzhiyun KIU_CLOCK,
56*4882a593Smuzhiyun FIR_CLOCK,
57*4882a593Smuzhiyun DSIU_CLOCK,
58*4882a593Smuzhiyun CSI_CLOCK,
59*4882a593Smuzhiyun PCIU_CLOCK,
60*4882a593Smuzhiyun HSP_CLOCK,
61*4882a593Smuzhiyun PCI_CLOCK,
62*4882a593Smuzhiyun CEU_CLOCK,
63*4882a593Smuzhiyun ETHER0_CLOCK,
64*4882a593Smuzhiyun ETHER1_CLOCK
65*4882a593Smuzhiyun } vr41xx_clock_t;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun extern void vr41xx_supply_clock(vr41xx_clock_t clock);
68*4882a593Smuzhiyun extern void vr41xx_mask_clock(vr41xx_clock_t clock);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * Interrupt Control Unit
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
74*4882a593Smuzhiyun extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int));
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define PIUINT_COMMAND 0x0040
77*4882a593Smuzhiyun #define PIUINT_DATA 0x0020
78*4882a593Smuzhiyun #define PIUINT_PAGE1 0x0010
79*4882a593Smuzhiyun #define PIUINT_PAGE0 0x0008
80*4882a593Smuzhiyun #define PIUINT_DATALOST 0x0004
81*4882a593Smuzhiyun #define PIUINT_STATUSCHANGE 0x0001
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun extern void vr41xx_enable_piuint(uint16_t mask);
84*4882a593Smuzhiyun extern void vr41xx_disable_piuint(uint16_t mask);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define AIUINT_INPUT_DMAEND 0x0800
87*4882a593Smuzhiyun #define AIUINT_INPUT_DMAHALT 0x0400
88*4882a593Smuzhiyun #define AIUINT_INPUT_DATALOST 0x0200
89*4882a593Smuzhiyun #define AIUINT_INPUT_DATA 0x0100
90*4882a593Smuzhiyun #define AIUINT_OUTPUT_DMAEND 0x0008
91*4882a593Smuzhiyun #define AIUINT_OUTPUT_DMAHALT 0x0004
92*4882a593Smuzhiyun #define AIUINT_OUTPUT_NODATA 0x0002
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun extern void vr41xx_enable_aiuint(uint16_t mask);
95*4882a593Smuzhiyun extern void vr41xx_disable_aiuint(uint16_t mask);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define KIUINT_DATALOST 0x0004
98*4882a593Smuzhiyun #define KIUINT_DATAREADY 0x0002
99*4882a593Smuzhiyun #define KIUINT_SCAN 0x0001
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun extern void vr41xx_enable_kiuint(uint16_t mask);
102*4882a593Smuzhiyun extern void vr41xx_disable_kiuint(uint16_t mask);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #define DSIUINT_CTS 0x0800
105*4882a593Smuzhiyun #define DSIUINT_RXERR 0x0400
106*4882a593Smuzhiyun #define DSIUINT_RX 0x0200
107*4882a593Smuzhiyun #define DSIUINT_TX 0x0100
108*4882a593Smuzhiyun #define DSIUINT_ALL 0x0f00
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun extern void vr41xx_enable_dsiuint(uint16_t mask);
111*4882a593Smuzhiyun extern void vr41xx_disable_dsiuint(uint16_t mask);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #define FIRINT_UNIT 0x0010
114*4882a593Smuzhiyun #define FIRINT_RX_DMAEND 0x0008
115*4882a593Smuzhiyun #define FIRINT_RX_DMAHALT 0x0004
116*4882a593Smuzhiyun #define FIRINT_TX_DMAEND 0x0002
117*4882a593Smuzhiyun #define FIRINT_TX_DMAHALT 0x0001
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun extern void vr41xx_enable_firint(uint16_t mask);
120*4882a593Smuzhiyun extern void vr41xx_disable_firint(uint16_t mask);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun extern void vr41xx_enable_pciint(void);
123*4882a593Smuzhiyun extern void vr41xx_disable_pciint(void);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun extern void vr41xx_enable_scuint(void);
126*4882a593Smuzhiyun extern void vr41xx_disable_scuint(void);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #define CSIINT_TX_DMAEND 0x0040
129*4882a593Smuzhiyun #define CSIINT_TX_DMAHALT 0x0020
130*4882a593Smuzhiyun #define CSIINT_TX_DATA 0x0010
131*4882a593Smuzhiyun #define CSIINT_TX_FIFOEMPTY 0x0008
132*4882a593Smuzhiyun #define CSIINT_RX_DMAEND 0x0004
133*4882a593Smuzhiyun #define CSIINT_RX_DMAHALT 0x0002
134*4882a593Smuzhiyun #define CSIINT_RX_FIFOEMPTY 0x0001
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun extern void vr41xx_enable_csiint(uint16_t mask);
137*4882a593Smuzhiyun extern void vr41xx_disable_csiint(uint16_t mask);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun extern void vr41xx_enable_bcuint(void);
140*4882a593Smuzhiyun extern void vr41xx_disable_bcuint(void);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
143*4882a593Smuzhiyun extern void vr41xx_siu_setup(void);
144*4882a593Smuzhiyun #else
vr41xx_siu_setup(void)145*4882a593Smuzhiyun static inline void vr41xx_siu_setup(void) {}
146*4882a593Smuzhiyun #endif
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun #endif /* __NEC_VR41XX_H */
149