1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/asm-mips/vr41xx/irq.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Interrupt numbers for NEC VR4100 series. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 1999 Michael Klar 8*4882a593Smuzhiyun * Copyright (C) 2001, 2002 Paul Mundt 9*4882a593Smuzhiyun * Copyright (C) 2002 MontaVista Software, Inc. 10*4882a593Smuzhiyun * Copyright (C) 2002 TimeSys Corp. 11*4882a593Smuzhiyun * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org> 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef __NEC_VR41XX_IRQ_H 14*4882a593Smuzhiyun #define __NEC_VR41XX_IRQ_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * CPU core Interrupt Numbers 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define MIPS_CPU_IRQ_BASE 0 20*4882a593Smuzhiyun #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) 21*4882a593Smuzhiyun #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) 22*4882a593Smuzhiyun #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) 23*4882a593Smuzhiyun #define INT0_IRQ MIPS_CPU_IRQ(2) 24*4882a593Smuzhiyun #define INT1_IRQ MIPS_CPU_IRQ(3) 25*4882a593Smuzhiyun #define INT2_IRQ MIPS_CPU_IRQ(4) 26*4882a593Smuzhiyun #define INT3_IRQ MIPS_CPU_IRQ(5) 27*4882a593Smuzhiyun #define INT4_IRQ MIPS_CPU_IRQ(6) 28*4882a593Smuzhiyun #define TIMER_IRQ MIPS_CPU_IRQ(7) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * SYINT1 Interrupt Numbers 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun #define SYSINT1_IRQ_BASE 8 34*4882a593Smuzhiyun #define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x)) 35*4882a593Smuzhiyun #define BATTRY_IRQ SYSINT1_IRQ(0) 36*4882a593Smuzhiyun #define POWER_IRQ SYSINT1_IRQ(1) 37*4882a593Smuzhiyun #define RTCLONG1_IRQ SYSINT1_IRQ(2) 38*4882a593Smuzhiyun #define ELAPSEDTIME_IRQ SYSINT1_IRQ(3) 39*4882a593Smuzhiyun /* RFU */ 40*4882a593Smuzhiyun #define PIU_IRQ SYSINT1_IRQ(5) 41*4882a593Smuzhiyun #define AIU_IRQ SYSINT1_IRQ(6) 42*4882a593Smuzhiyun #define KIU_IRQ SYSINT1_IRQ(7) 43*4882a593Smuzhiyun #define GIUINT_IRQ SYSINT1_IRQ(8) 44*4882a593Smuzhiyun #define SIU_IRQ SYSINT1_IRQ(9) 45*4882a593Smuzhiyun #define BUSERR_IRQ SYSINT1_IRQ(10) 46*4882a593Smuzhiyun #define SOFTINT_IRQ SYSINT1_IRQ(11) 47*4882a593Smuzhiyun #define CLKRUN_IRQ SYSINT1_IRQ(12) 48*4882a593Smuzhiyun #define DOZEPIU_IRQ SYSINT1_IRQ(13) 49*4882a593Smuzhiyun #define SYSINT1_IRQ_LAST DOZEPIU_IRQ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * SYSINT2 Interrupt Numbers 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define SYSINT2_IRQ_BASE 24 55*4882a593Smuzhiyun #define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x)) 56*4882a593Smuzhiyun #define RTCLONG2_IRQ SYSINT2_IRQ(0) 57*4882a593Smuzhiyun #define LED_IRQ SYSINT2_IRQ(1) 58*4882a593Smuzhiyun #define HSP_IRQ SYSINT2_IRQ(2) 59*4882a593Smuzhiyun #define TCLOCK_IRQ SYSINT2_IRQ(3) 60*4882a593Smuzhiyun #define FIR_IRQ SYSINT2_IRQ(4) 61*4882a593Smuzhiyun #define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */ 62*4882a593Smuzhiyun #define DSIU_IRQ SYSINT2_IRQ(5) 63*4882a593Smuzhiyun #define PCI_IRQ SYSINT2_IRQ(6) 64*4882a593Smuzhiyun #define SCU_IRQ SYSINT2_IRQ(7) 65*4882a593Smuzhiyun #define CSI_IRQ SYSINT2_IRQ(8) 66*4882a593Smuzhiyun #define BCU_IRQ SYSINT2_IRQ(9) 67*4882a593Smuzhiyun #define ETHERNET_IRQ SYSINT2_IRQ(10) 68*4882a593Smuzhiyun #define SYSINT2_IRQ_LAST ETHERNET_IRQ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * GIU Interrupt Numbers 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define GIU_IRQ_BASE 40 74*4882a593Smuzhiyun #define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */ 75*4882a593Smuzhiyun #define GIU_IRQ_LAST GIU_IRQ(31) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * VRC4173 Interrupt Numbers 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun #define VRC4173_IRQ_BASE 72 81*4882a593Smuzhiyun #define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x)) 82*4882a593Smuzhiyun #define VRC4173_USB_IRQ VRC4173_IRQ(0) 83*4882a593Smuzhiyun #define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1) 84*4882a593Smuzhiyun #define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2) 85*4882a593Smuzhiyun #define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3) 86*4882a593Smuzhiyun #define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4) 87*4882a593Smuzhiyun #define VRC4173_PIU_IRQ VRC4173_IRQ(5) 88*4882a593Smuzhiyun #define VRC4173_AIU_IRQ VRC4173_IRQ(6) 89*4882a593Smuzhiyun #define VRC4173_KIU_IRQ VRC4173_IRQ(7) 90*4882a593Smuzhiyun #define VRC4173_GIU_IRQ VRC4173_IRQ(8) 91*4882a593Smuzhiyun #define VRC4173_AC97_IRQ VRC4173_IRQ(9) 92*4882a593Smuzhiyun #define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10) 93*4882a593Smuzhiyun /* RFU */ 94*4882a593Smuzhiyun #define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13) 95*4882a593Smuzhiyun #define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* __NEC_VR41XX_IRQ_H */ 98