1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/asm-mips/txx9tmr.h 3*4882a593Smuzhiyun * TX39/TX49 timer controller definitions. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 6*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 7*4882a593Smuzhiyun * for more details. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_TXX9TMR_H 10*4882a593Smuzhiyun #define __ASM_TXX9TMR_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct txx9_tmr_reg { 15*4882a593Smuzhiyun u32 tcr; 16*4882a593Smuzhiyun u32 tisr; 17*4882a593Smuzhiyun u32 cpra; 18*4882a593Smuzhiyun u32 cprb; 19*4882a593Smuzhiyun u32 itmr; 20*4882a593Smuzhiyun u32 unused0[3]; 21*4882a593Smuzhiyun u32 ccdr; 22*4882a593Smuzhiyun u32 unused1[3]; 23*4882a593Smuzhiyun u32 pgmr; 24*4882a593Smuzhiyun u32 unused2[3]; 25*4882a593Smuzhiyun u32 wtmr; 26*4882a593Smuzhiyun u32 unused3[43]; 27*4882a593Smuzhiyun u32 trr; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* TMTCR : Timer Control */ 31*4882a593Smuzhiyun #define TXx9_TMTCR_TCE 0x00000080 32*4882a593Smuzhiyun #define TXx9_TMTCR_CCDE 0x00000040 33*4882a593Smuzhiyun #define TXx9_TMTCR_CRE 0x00000020 34*4882a593Smuzhiyun #define TXx9_TMTCR_ECES 0x00000008 35*4882a593Smuzhiyun #define TXx9_TMTCR_CCS 0x00000004 36*4882a593Smuzhiyun #define TXx9_TMTCR_TMODE_MASK 0x00000003 37*4882a593Smuzhiyun #define TXx9_TMTCR_TMODE_ITVL 0x00000000 38*4882a593Smuzhiyun #define TXx9_TMTCR_TMODE_PGEN 0x00000001 39*4882a593Smuzhiyun #define TXx9_TMTCR_TMODE_WDOG 0x00000002 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* TMTISR : Timer Int. Status */ 42*4882a593Smuzhiyun #define TXx9_TMTISR_TPIBS 0x00000004 43*4882a593Smuzhiyun #define TXx9_TMTISR_TPIAS 0x00000002 44*4882a593Smuzhiyun #define TXx9_TMTISR_TIIS 0x00000001 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* TMITMR : Interval Timer Mode */ 47*4882a593Smuzhiyun #define TXx9_TMITMR_TIIE 0x00008000 48*4882a593Smuzhiyun #define TXx9_TMITMR_TZCE 0x00000001 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* TMWTMR : Watchdog Timer Mode */ 51*4882a593Smuzhiyun #define TXx9_TMWTMR_TWIE 0x00008000 52*4882a593Smuzhiyun #define TXx9_TMWTMR_WDIS 0x00000080 53*4882a593Smuzhiyun #define TXx9_TMWTMR_TWC 0x00000001 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun void txx9_clocksource_init(unsigned long baseaddr, 56*4882a593Smuzhiyun unsigned int imbusclk); 57*4882a593Smuzhiyun void txx9_clockevent_init(unsigned long baseaddr, int irq, 58*4882a593Smuzhiyun unsigned int imbusclk); 59*4882a593Smuzhiyun void txx9_tmr_init(unsigned long baseaddr); 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #ifdef CONFIG_CPU_TX39XX 62*4882a593Smuzhiyun #define TXX9_TIMER_BITS 24 63*4882a593Smuzhiyun #else 64*4882a593Smuzhiyun #define TXX9_TIMER_BITS 32 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __ASM_TXX9TMR_H */ 68