1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Interface for smsc fdc48m81x Super IO chip 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: MontaVista Software, Inc. source@mvista.com 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under 7*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program 8*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express 9*4882a593Smuzhiyun * or implied. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Copyright (C) 2004 MontaVista Software Inc. 12*4882a593Smuzhiyun * Manish Lachwani, mlachwani@mvista.com 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _SMSC_FDC37M81X_H_ 16*4882a593Smuzhiyun #define _SMSC_FDC37M81X_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Common Registers */ 19*4882a593Smuzhiyun #define SMSC_FDC37M81X_CONFIG_INDEX 0x00 20*4882a593Smuzhiyun #define SMSC_FDC37M81X_CONFIG_DATA 0x01 21*4882a593Smuzhiyun #define SMSC_FDC37M81X_CONF 0x02 22*4882a593Smuzhiyun #define SMSC_FDC37M81X_INDEX 0x03 23*4882a593Smuzhiyun #define SMSC_FDC37M81X_DNUM 0x07 24*4882a593Smuzhiyun #define SMSC_FDC37M81X_DID 0x20 25*4882a593Smuzhiyun #define SMSC_FDC37M81X_DREV 0x21 26*4882a593Smuzhiyun #define SMSC_FDC37M81X_PCNT 0x22 27*4882a593Smuzhiyun #define SMSC_FDC37M81X_PMGT 0x23 28*4882a593Smuzhiyun #define SMSC_FDC37M81X_OSC 0x24 29*4882a593Smuzhiyun #define SMSC_FDC37M81X_CONFPA0 0x26 30*4882a593Smuzhiyun #define SMSC_FDC37M81X_CONFPA1 0x27 31*4882a593Smuzhiyun #define SMSC_FDC37M81X_TEST4 0x2B 32*4882a593Smuzhiyun #define SMSC_FDC37M81X_TEST5 0x2C 33*4882a593Smuzhiyun #define SMSC_FDC37M81X_TEST1 0x2D 34*4882a593Smuzhiyun #define SMSC_FDC37M81X_TEST2 0x2E 35*4882a593Smuzhiyun #define SMSC_FDC37M81X_TEST3 0x2F 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Logical device numbers */ 38*4882a593Smuzhiyun #define SMSC_FDC37M81X_FDD 0x00 39*4882a593Smuzhiyun #define SMSC_FDC37M81X_PARALLEL 0x03 40*4882a593Smuzhiyun #define SMSC_FDC37M81X_SERIAL1 0x04 41*4882a593Smuzhiyun #define SMSC_FDC37M81X_SERIAL2 0x05 42*4882a593Smuzhiyun #define SMSC_FDC37M81X_KBD 0x07 43*4882a593Smuzhiyun #define SMSC_FDC37M81X_AUXIO 0x08 44*4882a593Smuzhiyun #define SMSC_FDC37M81X_NONE 0xff 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Logical device Config Registers */ 47*4882a593Smuzhiyun #define SMSC_FDC37M81X_ACTIVE 0x30 48*4882a593Smuzhiyun #define SMSC_FDC37M81X_BASEADDR0 0x60 49*4882a593Smuzhiyun #define SMSC_FDC37M81X_BASEADDR1 0x61 50*4882a593Smuzhiyun #define SMSC_FDC37M81X_INT 0x70 51*4882a593Smuzhiyun #define SMSC_FDC37M81X_INT2 0x72 52*4882a593Smuzhiyun #define SMSC_FDC37M81X_LDCR_F0 0xF0 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Chip Config Values */ 55*4882a593Smuzhiyun #define SMSC_FDC37M81X_CONFIG_ENTER 0x55 56*4882a593Smuzhiyun #define SMSC_FDC37M81X_CONFIG_EXIT 0xaa 57*4882a593Smuzhiyun #define SMSC_FDC37M81X_CHIP_ID 0x4d 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun unsigned long smsc_fdc37m81x_init(unsigned long port); 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun void smsc_fdc37m81x_config_beg(void); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun void smsc_fdc37m81x_config_end(void); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun u8 smsc_fdc37m81x_config_get(u8 reg); 66*4882a593Smuzhiyun void smsc_fdc37m81x_config_set(u8 reg, u8 val); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69