1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Definitions for RBTX4939 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright TOSHIBA CORPORATION 2005-2006 5*4882a593Smuzhiyun * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the 6*4882a593Smuzhiyun * terms of the GNU General Public License version 2. This program is 7*4882a593Smuzhiyun * licensed "as is" without any warranty of any kind, whether express 8*4882a593Smuzhiyun * or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ASM_TXX9_RBTX4939_H 11*4882a593Smuzhiyun #define __ASM_TXX9_RBTX4939_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/addrspace.h> 14*4882a593Smuzhiyun #include <asm/txx9irq.h> 15*4882a593Smuzhiyun #include <asm/txx9/generic.h> 16*4882a593Smuzhiyun #include <asm/txx9/tx4939.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Address map */ 19*4882a593Smuzhiyun #define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) 20*4882a593Smuzhiyun #define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) 21*4882a593Smuzhiyun #define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002) 22*4882a593Smuzhiyun #define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004) 23*4882a593Smuzhiyun #define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006) 24*4882a593Smuzhiyun #define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008) 25*4882a593Smuzhiyun #define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a) 26*4882a593Smuzhiyun #define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000) 27*4882a593Smuzhiyun #define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002) 28*4882a593Smuzhiyun #define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004) 29*4882a593Smuzhiyun #define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000) 30*4882a593Smuzhiyun #define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002) 31*4882a593Smuzhiyun #define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004) 32*4882a593Smuzhiyun #define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006) 33*4882a593Smuzhiyun #define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000) 34*4882a593Smuzhiyun #define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000) 35*4882a593Smuzhiyun #define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002) 36*4882a593Smuzhiyun #define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004) 37*4882a593Smuzhiyun #define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006) 38*4882a593Smuzhiyun #define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008) 39*4882a593Smuzhiyun #define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a) 40*4882a593Smuzhiyun #define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000) 41*4882a593Smuzhiyun #define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002) 42*4882a593Smuzhiyun #define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004) 43*4882a593Smuzhiyun #define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006) 44*4882a593Smuzhiyun #define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008) 45*4882a593Smuzhiyun #define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a) 46*4882a593Smuzhiyun #define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c) 47*4882a593Smuzhiyun #define RBTX4939_7SEG_ADDR(s, ch) \ 48*4882a593Smuzhiyun (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2) 49*4882a593Smuzhiyun #define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000) 50*4882a593Smuzhiyun #define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002) 51*4882a593Smuzhiyun #define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004) 52*4882a593Smuzhiyun #define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Ethernet port address */ 55*4882a593Smuzhiyun #define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* bits for IEN/IPOL/IFAC */ 58*4882a593Smuzhiyun #define RBTX4938_INTB_ISA0 0 59*4882a593Smuzhiyun #define RBTX4938_INTB_ISA11 1 60*4882a593Smuzhiyun #define RBTX4938_INTB_ISA12 2 61*4882a593Smuzhiyun #define RBTX4938_INTB_ISA15 3 62*4882a593Smuzhiyun #define RBTX4938_INTB_I2S 4 63*4882a593Smuzhiyun #define RBTX4938_INTB_SW 5 64*4882a593Smuzhiyun #define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0) 65*4882a593Smuzhiyun #define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11) 66*4882a593Smuzhiyun #define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12) 67*4882a593Smuzhiyun #define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15) 68*4882a593Smuzhiyun #define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S) 69*4882a593Smuzhiyun #define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* bits for PE1,PE2,PE3 */ 72*4882a593Smuzhiyun #define RBTX4939_PE1_ATA(ch) (0x01 << (ch)) 73*4882a593Smuzhiyun #define RBTX4939_PE1_RMII(ch) (0x04 << (ch)) 74*4882a593Smuzhiyun #define RBTX4939_PE2_SIO0 0x01 75*4882a593Smuzhiyun #define RBTX4939_PE2_SIO2 0x02 76*4882a593Smuzhiyun #define RBTX4939_PE2_SIO3 0x04 77*4882a593Smuzhiyun #define RBTX4939_PE2_CIR 0x08 78*4882a593Smuzhiyun #define RBTX4939_PE2_SPI 0x10 79*4882a593Smuzhiyun #define RBTX4939_PE2_GPIO 0x20 80*4882a593Smuzhiyun #define RBTX4939_PE3_VP 0x01 81*4882a593Smuzhiyun #define RBTX4939_PE3_VP_P 0x02 82*4882a593Smuzhiyun #define RBTX4939_PE3_VP_S 0x04 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR) 85*4882a593Smuzhiyun #define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR) 86*4882a593Smuzhiyun #define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR) 87*4882a593Smuzhiyun #define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR) 88*4882a593Smuzhiyun #define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR) 89*4882a593Smuzhiyun #define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR) 90*4882a593Smuzhiyun #define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR) 91*4882a593Smuzhiyun #define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR) 92*4882a593Smuzhiyun #define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR) 93*4882a593Smuzhiyun #define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR) 94*4882a593Smuzhiyun #define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR) 95*4882a593Smuzhiyun #define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR) 96*4882a593Smuzhiyun #define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR) 97*4882a593Smuzhiyun #define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR) 98*4882a593Smuzhiyun #define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR) 99*4882a593Smuzhiyun #define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR) 100*4882a593Smuzhiyun #define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR) 101*4882a593Smuzhiyun #define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR) 102*4882a593Smuzhiyun #define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR) 103*4882a593Smuzhiyun #define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR) 104*4882a593Smuzhiyun #define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR) 105*4882a593Smuzhiyun #define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR) 106*4882a593Smuzhiyun #define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR) 107*4882a593Smuzhiyun #define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR) 108*4882a593Smuzhiyun #define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR) 109*4882a593Smuzhiyun #define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR) 110*4882a593Smuzhiyun #define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR) 111*4882a593Smuzhiyun #define rbtx4939_7seg_addr(s, ch) \ 112*4882a593Smuzhiyun ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch)) 113*4882a593Smuzhiyun #define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR) 114*4882a593Smuzhiyun #define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR) 115*4882a593Smuzhiyun #define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* 118*4882a593Smuzhiyun * IRQ mappings 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun #define RBTX4939_NR_IRQ_IOC 8 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR) 123*4882a593Smuzhiyun #define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* IOC (ISA, etc) */ 126*4882a593Smuzhiyun #define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0)) 127*4882a593Smuzhiyun /* Onboard 10M Ether */ 128*4882a593Smuzhiyun #define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1)) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun void rbtx4939_prom_init(void); 131*4882a593Smuzhiyun void rbtx4939_irq_setup(void); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun struct mtd_partition; 134*4882a593Smuzhiyun struct map_info; 135*4882a593Smuzhiyun struct rbtx4939_flash_data { 136*4882a593Smuzhiyun unsigned int width; 137*4882a593Smuzhiyun unsigned int nr_parts; 138*4882a593Smuzhiyun struct mtd_partition *parts; 139*4882a593Smuzhiyun void (*map_init)(struct map_info *map); 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif /* __ASM_TXX9_RBTX4939_H */ 143