1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Definitions for TX4937/TX4938 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the 5*4882a593Smuzhiyun * terms of the GNU General Public License version 2. This program is 6*4882a593Smuzhiyun * licensed "as is" without any warranty of any kind, whether express 7*4882a593Smuzhiyun * or implied. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __ASM_TXX9_RBTX4938_H 12*4882a593Smuzhiyun #define __ASM_TXX9_RBTX4938_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <asm/addrspace.h> 15*4882a593Smuzhiyun #include <asm/txx9irq.h> 16*4882a593Smuzhiyun #include <asm/txx9/tx4938.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Address map */ 19*4882a593Smuzhiyun #define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000) 20*4882a593Smuzhiyun #define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002) 21*4882a593Smuzhiyun #define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004) 22*4882a593Smuzhiyun #define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006) 23*4882a593Smuzhiyun #define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008) 24*4882a593Smuzhiyun #define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) 25*4882a593Smuzhiyun #define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002) 26*4882a593Smuzhiyun #define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004) 27*4882a593Smuzhiyun #define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) 28*4882a593Smuzhiyun #define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002) 29*4882a593Smuzhiyun #define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004) 30*4882a593Smuzhiyun #define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) 31*4882a593Smuzhiyun #define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008) 32*4882a593Smuzhiyun #define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a) 33*4882a593Smuzhiyun #define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c) 34*4882a593Smuzhiyun #define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) 35*4882a593Smuzhiyun #define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000) 36*4882a593Smuzhiyun #define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002) 37*4882a593Smuzhiyun #define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008) 38*4882a593Smuzhiyun #define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a) 39*4882a593Smuzhiyun #define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000) 40*4882a593Smuzhiyun #define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002) 41*4882a593Smuzhiyun #define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004) 42*4882a593Smuzhiyun #define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Ethernet port address (Jumperless Mode (W12:Open)) */ 45*4882a593Smuzhiyun #define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* bits for ISTAT/IMASK/IMSTAT */ 48*4882a593Smuzhiyun #define RBTX4938_INTB_PCID 0 49*4882a593Smuzhiyun #define RBTX4938_INTB_PCIC 1 50*4882a593Smuzhiyun #define RBTX4938_INTB_PCIB 2 51*4882a593Smuzhiyun #define RBTX4938_INTB_PCIA 3 52*4882a593Smuzhiyun #define RBTX4938_INTB_RTC 4 53*4882a593Smuzhiyun #define RBTX4938_INTB_ATA 5 54*4882a593Smuzhiyun #define RBTX4938_INTB_MODEM 6 55*4882a593Smuzhiyun #define RBTX4938_INTB_SWINT 7 56*4882a593Smuzhiyun #define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) 57*4882a593Smuzhiyun #define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) 58*4882a593Smuzhiyun #define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) 59*4882a593Smuzhiyun #define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) 60*4882a593Smuzhiyun #define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) 61*4882a593Smuzhiyun #define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) 62*4882a593Smuzhiyun #define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) 63*4882a593Smuzhiyun #define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) 66*4882a593Smuzhiyun #define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) 67*4882a593Smuzhiyun #define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) 68*4882a593Smuzhiyun #define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) 69*4882a593Smuzhiyun #define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) 70*4882a593Smuzhiyun #define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) 71*4882a593Smuzhiyun #define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) 72*4882a593Smuzhiyun #define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) 73*4882a593Smuzhiyun #define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) 74*4882a593Smuzhiyun #define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) 75*4882a593Smuzhiyun #define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) 76*4882a593Smuzhiyun #define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) 77*4882a593Smuzhiyun #define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) 78*4882a593Smuzhiyun #define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) 79*4882a593Smuzhiyun #define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) 80*4882a593Smuzhiyun #define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) 81*4882a593Smuzhiyun #define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) 82*4882a593Smuzhiyun #define rbtx4938_softresetlock_addr \ 83*4882a593Smuzhiyun ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) 84*4882a593Smuzhiyun #define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * IRQ mappings 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define RBTX4938_SOFT_INT0 0 /* not used */ 91*4882a593Smuzhiyun #define RBTX4938_SOFT_INT1 1 /* not used */ 92*4882a593Smuzhiyun #define RBTX4938_IRC_INT 2 93*4882a593Smuzhiyun #define RBTX4938_TIMER_INT 7 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* These are the virtual IRQ numbers, we divide all IRQ's into 96*4882a593Smuzhiyun * 'spaces', the 'space' determines where and how to enable/disable 97*4882a593Smuzhiyun * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new 98*4882a593Smuzhiyun * IRQ hardware is supported. 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun #define RBTX4938_NR_IRQ_IOC 8 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC TXX9_IRQ_BASE 103*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR) 104*4882a593Smuzhiyun #define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) 107*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) 108*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) 109*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) 110*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) 111*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) 112*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) 113*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) 114*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) 115*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) 116*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) 117*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) 118*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) 119*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) 120*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) 121*4882a593Smuzhiyun #define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) 122*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) 123*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) 124*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) 125*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) 126*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) 127*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) 128*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) 129*4882a593Smuzhiyun #define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* IOC (PCI, etc) */ 133*4882a593Smuzhiyun #define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0)) 134*4882a593Smuzhiyun /* Onboard 10M Ether */ 135*4882a593Smuzhiyun #define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1)) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) 138*4882a593Smuzhiyun #define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun void rbtx4938_prom_init(void); 141*4882a593Smuzhiyun void rbtx4938_irq_setup(void); 142*4882a593Smuzhiyun struct pci_dev; 143*4882a593Smuzhiyun int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #endif /* __ASM_TXX9_RBTX4938_H */ 146