1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_TLB_H 3*4882a593Smuzhiyun #define __ASM_TLB_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/cpu-features.h> 6*4882a593Smuzhiyun #include <asm/mipsregs.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define _UNIQUE_ENTRYHI(base, idx) \ 9*4882a593Smuzhiyun (((base) + ((idx) << (PAGE_SHIFT + 1))) | \ 10*4882a593Smuzhiyun (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) 11*4882a593Smuzhiyun #define UNIQUE_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG0, idx) 12*4882a593Smuzhiyun #define UNIQUE_GUEST_ENTRYHI(idx) _UNIQUE_ENTRYHI(CKSEG1, idx) 13*4882a593Smuzhiyun num_wired_entries(void)14*4882a593Smuzhiyunstatic inline unsigned int num_wired_entries(void) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun unsigned int wired = read_c0_wired(); 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun if (cpu_has_mips_r6) 19*4882a593Smuzhiyun wired &= MIPSR6_WIRED_WIRED; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun return wired; 22*4882a593Smuzhiyun } 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <asm-generic/tlb.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif /* __ASM_TLB_H */ 27