1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2001, 2002, MontaVista Software Inc. 4*4882a593Smuzhiyun * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 5*4882a593Smuzhiyun * Copyright (c) 2003 Maciej W. Rozycki 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * include/asm-mips/time.h 8*4882a593Smuzhiyun * header file for the new style time.c file and time services. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef _ASM_TIME_H 11*4882a593Smuzhiyun #define _ASM_TIME_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/rtc.h> 14*4882a593Smuzhiyun #include <linux/spinlock.h> 15*4882a593Smuzhiyun #include <linux/clockchips.h> 16*4882a593Smuzhiyun #include <linux/clocksource.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun extern spinlock_t rtc_lock; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * board specific routines required by time_init(). 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun extern void plat_time_init(void); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * mips_hpt_frequency - must be set if you intend to use an R4k-compatible 27*4882a593Smuzhiyun * counter as a timer interrupt source. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun extern unsigned int mips_hpt_frequency; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * The performance counter IRQ on MIPS is a close relative to the timer IRQ 33*4882a593Smuzhiyun * so it lives here. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun extern int (*perf_irq)(void); 36*4882a593Smuzhiyun extern int __weak get_c0_perfcount_int(void); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Initialize the calling CPU's compare interrupt as clockevent device 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun extern unsigned int get_c0_compare_int(void); 42*4882a593Smuzhiyun extern int r4k_clockevent_init(void); 43*4882a593Smuzhiyun mips_clockevent_init(void)44*4882a593Smuzhiyunstatic inline int mips_clockevent_init(void) 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun #ifdef CONFIG_CEVT_R4K 47*4882a593Smuzhiyun return r4k_clockevent_init(); 48*4882a593Smuzhiyun #else 49*4882a593Smuzhiyun return -ENXIO; 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * Initialize the count register as a clocksource 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun extern int init_r4k_clocksource(void); 57*4882a593Smuzhiyun init_mips_clocksource(void)58*4882a593Smuzhiyunstatic inline int init_mips_clocksource(void) 59*4882a593Smuzhiyun { 60*4882a593Smuzhiyun #ifdef CONFIG_CSRC_R4K 61*4882a593Smuzhiyun return init_r4k_clocksource(); 62*4882a593Smuzhiyun #else 63*4882a593Smuzhiyun return 0; 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun } 66*4882a593Smuzhiyun clockevent_set_clock(struct clock_event_device * cd,unsigned int clock)67*4882a593Smuzhiyunstatic inline void clockevent_set_clock(struct clock_event_device *cd, 68*4882a593Smuzhiyun unsigned int clock) 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun clockevents_calc_mult_shift(cd, clock, 4); 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* _ASM_TIME_H */ 74