xref: /OK3568_Linux_fs/kernel/arch/mips/include/asm/switch_to.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun  * License.  See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun  * for more details.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7*4882a593Smuzhiyun  * Copyright (C) 1996 by Paul M. Antoine
8*4882a593Smuzhiyun  * Copyright (C) 1999 Silicon Graphics
9*4882a593Smuzhiyun  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10*4882a593Smuzhiyun  * Copyright (C) 2000 MIPS Technologies, Inc.
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun #ifndef _ASM_SWITCH_TO_H
13*4882a593Smuzhiyun #define _ASM_SWITCH_TO_H
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <asm/cpu-features.h>
16*4882a593Smuzhiyun #include <asm/watch.h>
17*4882a593Smuzhiyun #include <asm/dsp.h>
18*4882a593Smuzhiyun #include <asm/cop2.h>
19*4882a593Smuzhiyun #include <asm/fpu.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun struct task_struct;
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /**
24*4882a593Smuzhiyun  * resume - resume execution of a task
25*4882a593Smuzhiyun  * @prev:	The task previously executed.
26*4882a593Smuzhiyun  * @next:	The task to begin executing.
27*4882a593Smuzhiyun  * @next_ti:	task_thread_info(next).
28*4882a593Smuzhiyun  *
29*4882a593Smuzhiyun  * This function is used whilst scheduling to save the context of prev & load
30*4882a593Smuzhiyun  * the context of next. Returns prev.
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun extern asmlinkage struct task_struct *resume(struct task_struct *prev,
33*4882a593Smuzhiyun 		struct task_struct *next, struct thread_info *next_ti);
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun extern unsigned int ll_bit;
36*4882a593Smuzhiyun extern struct task_struct *ll_task;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #ifdef CONFIG_MIPS_MT_FPAFF
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun  * Handle the scheduler resume end of FPU affinity management.	We do this
42*4882a593Smuzhiyun  * inline to try to keep the overhead down. If we have been forced to run on
43*4882a593Smuzhiyun  * a "CPU" with an FPU because of a previous high level of FP computation,
44*4882a593Smuzhiyun  * but did not actually use the FPU during the most recent time-slice (CU1
45*4882a593Smuzhiyun  * isn't set), we undo the restriction on cpus_mask.
46*4882a593Smuzhiyun  *
47*4882a593Smuzhiyun  * We're not calling set_cpus_allowed() here, because we have no need to
48*4882a593Smuzhiyun  * force prompt migration - we're already switching the current CPU to a
49*4882a593Smuzhiyun  * different thread.
50*4882a593Smuzhiyun  */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define __mips_mt_fpaff_switch_to(prev)					\
53*4882a593Smuzhiyun do {									\
54*4882a593Smuzhiyun 	struct thread_info *__prev_ti = task_thread_info(prev);		\
55*4882a593Smuzhiyun 									\
56*4882a593Smuzhiyun 	if (cpu_has_fpu &&						\
57*4882a593Smuzhiyun 	    test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&		\
58*4882a593Smuzhiyun 	    (!(KSTK_STATUS(prev) & ST0_CU1))) {				\
59*4882a593Smuzhiyun 		clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);		\
60*4882a593Smuzhiyun 		prev->cpus_mask = prev->thread.user_cpus_allowed;	\
61*4882a593Smuzhiyun 	}								\
62*4882a593Smuzhiyun 	next->thread.emulated_fp = 0;					\
63*4882a593Smuzhiyun } while(0)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #else
66*4882a593Smuzhiyun #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
67*4882a593Smuzhiyun #endif
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun  * Clear LLBit during context switches on MIPSr5+ such that eretnc can be used
71*4882a593Smuzhiyun  * unconditionally when returning to userland in entry.S.
72*4882a593Smuzhiyun  */
73*4882a593Smuzhiyun #define __clear_r5_hw_ll_bit() do {					\
74*4882a593Smuzhiyun 	if (cpu_has_mips_r5 || cpu_has_mips_r6)				\
75*4882a593Smuzhiyun 		write_c0_lladdr(0);					\
76*4882a593Smuzhiyun } while (0)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define __clear_software_ll_bit() do {					\
79*4882a593Smuzhiyun 	if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)	\
80*4882a593Smuzhiyun 		ll_bit = 0;						\
81*4882a593Smuzhiyun } while (0)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun  * Check FCSR for any unmasked exceptions pending set with `ptrace',
85*4882a593Smuzhiyun  * clear them and send a signal.
86*4882a593Smuzhiyun  */
87*4882a593Smuzhiyun #ifdef CONFIG_MIPS_FP_SUPPORT
88*4882a593Smuzhiyun # define __sanitize_fcr31(next)						\
89*4882a593Smuzhiyun do {									\
90*4882a593Smuzhiyun 	unsigned long fcr31 = mask_fcr31_x(next->thread.fpu.fcr31);	\
91*4882a593Smuzhiyun 	void __user *pc;						\
92*4882a593Smuzhiyun 									\
93*4882a593Smuzhiyun 	if (unlikely(fcr31)) {						\
94*4882a593Smuzhiyun 		pc = (void __user *)task_pt_regs(next)->cp0_epc;	\
95*4882a593Smuzhiyun 		next->thread.fpu.fcr31 &= ~fcr31;			\
96*4882a593Smuzhiyun 		force_fcr31_sig(fcr31, pc, next);			\
97*4882a593Smuzhiyun 	}								\
98*4882a593Smuzhiyun } while (0)
99*4882a593Smuzhiyun #else
100*4882a593Smuzhiyun # define __sanitize_fcr31(next)
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun  * For newly created kernel threads switch_to() will return to
105*4882a593Smuzhiyun  * ret_from_kernel_thread, newly created user threads to ret_from_fork.
106*4882a593Smuzhiyun  * That is, everything following resume() will be skipped for new threads.
107*4882a593Smuzhiyun  * So everything that matters to new threads should be placed before resume().
108*4882a593Smuzhiyun  */
109*4882a593Smuzhiyun #define switch_to(prev, next, last)					\
110*4882a593Smuzhiyun do {									\
111*4882a593Smuzhiyun 	__mips_mt_fpaff_switch_to(prev);				\
112*4882a593Smuzhiyun 	lose_fpu_inatomic(1, prev);					\
113*4882a593Smuzhiyun 	if (tsk_used_math(next))					\
114*4882a593Smuzhiyun 		__sanitize_fcr31(next);					\
115*4882a593Smuzhiyun 	if (cpu_has_dsp) {						\
116*4882a593Smuzhiyun 		__save_dsp(prev);					\
117*4882a593Smuzhiyun 		__restore_dsp(next);					\
118*4882a593Smuzhiyun 	}								\
119*4882a593Smuzhiyun 	if (cop2_present) {						\
120*4882a593Smuzhiyun 		u32 status = read_c0_status();				\
121*4882a593Smuzhiyun 									\
122*4882a593Smuzhiyun 		set_c0_status(ST0_CU2);					\
123*4882a593Smuzhiyun 		if ((KSTK_STATUS(prev) & ST0_CU2)) {			\
124*4882a593Smuzhiyun 			if (cop2_lazy_restore)				\
125*4882a593Smuzhiyun 				KSTK_STATUS(prev) &= ~ST0_CU2;		\
126*4882a593Smuzhiyun 			cop2_save(prev);				\
127*4882a593Smuzhiyun 		}							\
128*4882a593Smuzhiyun 		if (KSTK_STATUS(next) & ST0_CU2 &&			\
129*4882a593Smuzhiyun 		    !cop2_lazy_restore) {				\
130*4882a593Smuzhiyun 			cop2_restore(next);				\
131*4882a593Smuzhiyun 		}							\
132*4882a593Smuzhiyun 		write_c0_status(status);				\
133*4882a593Smuzhiyun 	}								\
134*4882a593Smuzhiyun 	__clear_r5_hw_ll_bit();						\
135*4882a593Smuzhiyun 	__clear_software_ll_bit();					\
136*4882a593Smuzhiyun 	if (cpu_has_userlocal)						\
137*4882a593Smuzhiyun 		write_c0_userlocal(task_thread_info(next)->tp_value);	\
138*4882a593Smuzhiyun 	__restore_watch(next);						\
139*4882a593Smuzhiyun 	(last) = resume(prev, next, task_thread_info(next));		\
140*4882a593Smuzhiyun } while (0)
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #endif /* _ASM_SWITCH_TO_H */
143