1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Derived from IRIX <sys/SN/nmi.h>, Revision 1.5. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ASM_SN_NMI_H 11*4882a593Smuzhiyun #define __ASM_SN_NMI_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/sn/addrs.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * The launch data structure resides at a fixed place in each node's memory 17*4882a593Smuzhiyun * and is used to communicate between the master processor and the slave 18*4882a593Smuzhiyun * processors. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * The master stores launch parameters in the launch structure 21*4882a593Smuzhiyun * corresponding to a target processor that is in a slave loop, then sends 22*4882a593Smuzhiyun * an interrupt to the slave processor. The slave calls the desired 23*4882a593Smuzhiyun * function, followed by an optional rendezvous function, then returns to 24*4882a593Smuzhiyun * the slave loop. The master does not wait for the slaves before 25*4882a593Smuzhiyun * returning. 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * There is an array of launch structures, one per CPU on the node. One 28*4882a593Smuzhiyun * interrupt level is used per CPU. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define NMI_MAGIC 0x48414d4d455201 32*4882a593Smuzhiyun #define NMI_SIZEOF 0x40 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */ 35*4882a593Smuzhiyun #define NMI_OFF_FLAGS 0x08 36*4882a593Smuzhiyun #define NMI_OFF_CALL 0x10 37*4882a593Smuzhiyun #define NMI_OFF_CALLC 0x18 38*4882a593Smuzhiyun #define NMI_OFF_CALLPARM 0x20 39*4882a593Smuzhiyun #define NMI_OFF_GMASTER 0x28 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * The NMI routine is called only if the complement address is 43*4882a593Smuzhiyun * correct. 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * Before control is transferred to a routine, the complement address 46*4882a593Smuzhiyun * is zeroed (invalidated) to prevent an accidental call from a spurious 47*4882a593Smuzhiyun * interrupt. 48*4882a593Smuzhiyun * 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun typedef struct nmi_s { 54*4882a593Smuzhiyun volatile unsigned long magic; /* Magic number */ 55*4882a593Smuzhiyun volatile unsigned long flags; /* Combination of flags above */ 56*4882a593Smuzhiyun volatile void *call_addr; /* Routine for slave to call */ 57*4882a593Smuzhiyun volatile void *call_addr_c; /* 1's complement of address */ 58*4882a593Smuzhiyun volatile void *call_parm; /* Single parm passed to call */ 59*4882a593Smuzhiyun volatile unsigned long gmaster; /* Flag true only on global master*/ 60*4882a593Smuzhiyun } nmi_t; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Following definitions are needed both in the prom & the kernel 65*4882a593Smuzhiyun * to identify the format of the nmi cpu register save area in the 66*4882a593Smuzhiyun * low memory on each node. 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct reg_struct { 71*4882a593Smuzhiyun unsigned long gpr[32]; 72*4882a593Smuzhiyun unsigned long sr; 73*4882a593Smuzhiyun unsigned long cause; 74*4882a593Smuzhiyun unsigned long epc; 75*4882a593Smuzhiyun unsigned long badva; 76*4882a593Smuzhiyun unsigned long error_epc; 77*4882a593Smuzhiyun unsigned long cache_err; 78*4882a593Smuzhiyun unsigned long nmi_sr; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* These are the assembly language offsets into the reg_struct structure */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define R0_OFF 0x0 86*4882a593Smuzhiyun #define R1_OFF 0x8 87*4882a593Smuzhiyun #define R2_OFF 0x10 88*4882a593Smuzhiyun #define R3_OFF 0x18 89*4882a593Smuzhiyun #define R4_OFF 0x20 90*4882a593Smuzhiyun #define R5_OFF 0x28 91*4882a593Smuzhiyun #define R6_OFF 0x30 92*4882a593Smuzhiyun #define R7_OFF 0x38 93*4882a593Smuzhiyun #define R8_OFF 0x40 94*4882a593Smuzhiyun #define R9_OFF 0x48 95*4882a593Smuzhiyun #define R10_OFF 0x50 96*4882a593Smuzhiyun #define R11_OFF 0x58 97*4882a593Smuzhiyun #define R12_OFF 0x60 98*4882a593Smuzhiyun #define R13_OFF 0x68 99*4882a593Smuzhiyun #define R14_OFF 0x70 100*4882a593Smuzhiyun #define R15_OFF 0x78 101*4882a593Smuzhiyun #define R16_OFF 0x80 102*4882a593Smuzhiyun #define R17_OFF 0x88 103*4882a593Smuzhiyun #define R18_OFF 0x90 104*4882a593Smuzhiyun #define R19_OFF 0x98 105*4882a593Smuzhiyun #define R20_OFF 0xa0 106*4882a593Smuzhiyun #define R21_OFF 0xa8 107*4882a593Smuzhiyun #define R22_OFF 0xb0 108*4882a593Smuzhiyun #define R23_OFF 0xb8 109*4882a593Smuzhiyun #define R24_OFF 0xc0 110*4882a593Smuzhiyun #define R25_OFF 0xc8 111*4882a593Smuzhiyun #define R26_OFF 0xd0 112*4882a593Smuzhiyun #define R27_OFF 0xd8 113*4882a593Smuzhiyun #define R28_OFF 0xe0 114*4882a593Smuzhiyun #define R29_OFF 0xe8 115*4882a593Smuzhiyun #define R30_OFF 0xf0 116*4882a593Smuzhiyun #define R31_OFF 0xf8 117*4882a593Smuzhiyun #define SR_OFF 0x100 118*4882a593Smuzhiyun #define CAUSE_OFF 0x108 119*4882a593Smuzhiyun #define EPC_OFF 0x110 120*4882a593Smuzhiyun #define BADVA_OFF 0x118 121*4882a593Smuzhiyun #define ERROR_EPC_OFF 0x120 122*4882a593Smuzhiyun #define CACHE_ERR_OFF 0x128 123*4882a593Smuzhiyun #define NMISR_OFF 0x130 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #endif /* __ASM_SN_NMI_H */ 126