xref: /OK3568_Linux_fs/kernel/arch/mips/include/asm/sibyte/sb1250_syncser.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*  *********************************************************************
3*4882a593Smuzhiyun     *  SB1250 Board Support Package
4*4882a593Smuzhiyun     *
5*4882a593Smuzhiyun     *  Synchronous Serial Constants		 File: sb1250_syncser.h
6*4882a593Smuzhiyun     *
7*4882a593Smuzhiyun     *  This module contains constants and macros useful for
8*4882a593Smuzhiyun     *  manipulating the SB1250's Synchronous Serial
9*4882a593Smuzhiyun     *
10*4882a593Smuzhiyun     *  SB1250 specification level:  User's manual 1/02/02
11*4882a593Smuzhiyun     *
12*4882a593Smuzhiyun     *********************************************************************
13*4882a593Smuzhiyun     *
14*4882a593Smuzhiyun     *  Copyright 2000,2001,2002,2003
15*4882a593Smuzhiyun     *  Broadcom Corporation. All rights reserved.
16*4882a593Smuzhiyun     *
17*4882a593Smuzhiyun     ********************************************************************* */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #ifndef _SB1250_SYNCSER_H
21*4882a593Smuzhiyun #define _SB1250_SYNCSER_H
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <asm/sibyte/sb1250_defs.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun  * Serial Mode Configuration Register
27*4882a593Smuzhiyun  */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define M_SYNCSER_CRC_MODE		   _SB_MAKEMASK1(0)
30*4882a593Smuzhiyun #define M_SYNCSER_MSB_FIRST		   _SB_MAKEMASK1(1)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define S_SYNCSER_FLAG_NUM		   2
33*4882a593Smuzhiyun #define M_SYNCSER_FLAG_NUM		   _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
34*4882a593Smuzhiyun #define V_SYNCSER_FLAG_NUM		   _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define M_SYNCSER_FLAG_EN		   _SB_MAKEMASK1(6)
37*4882a593Smuzhiyun #define M_SYNCSER_HDLC_EN		   _SB_MAKEMASK1(7)
38*4882a593Smuzhiyun #define M_SYNCSER_LOOP_MODE		   _SB_MAKEMASK1(8)
39*4882a593Smuzhiyun #define M_SYNCSER_LOOPBACK		   _SB_MAKEMASK1(9)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun  * Serial Clock Source and Line Interface Mode Register
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define M_SYNCSER_RXCLK_INV		   _SB_MAKEMASK1(0)
46*4882a593Smuzhiyun #define M_SYNCSER_RXCLK_EXT		   _SB_MAKEMASK1(1)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define S_SYNCSER_RXSYNC_DLY		   2
49*4882a593Smuzhiyun #define M_SYNCSER_RXSYNC_DLY		   _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
50*4882a593Smuzhiyun #define V_SYNCSER_RXSYNC_DLY(x)		   _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define M_SYNCSER_RXSYNC_LOW		   _SB_MAKEMASK1(4)
53*4882a593Smuzhiyun #define M_SYNCSER_RXSTRB_LOW		   _SB_MAKEMASK1(5)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define M_SYNCSER_RXSYNC_EDGE		   _SB_MAKEMASK1(6)
56*4882a593Smuzhiyun #define M_SYNCSER_RXSYNC_INT		   _SB_MAKEMASK1(7)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define M_SYNCSER_TXCLK_INV		   _SB_MAKEMASK1(8)
59*4882a593Smuzhiyun #define M_SYNCSER_TXCLK_EXT		   _SB_MAKEMASK1(9)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define S_SYNCSER_TXSYNC_DLY		   10
62*4882a593Smuzhiyun #define M_SYNCSER_TXSYNC_DLY		   _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
63*4882a593Smuzhiyun #define V_SYNCSER_TXSYNC_DLY(x)		   _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define M_SYNCSER_TXSYNC_LOW		   _SB_MAKEMASK1(12)
66*4882a593Smuzhiyun #define M_SYNCSER_TXSTRB_LOW		   _SB_MAKEMASK1(13)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define M_SYNCSER_TXSYNC_EDGE		   _SB_MAKEMASK1(14)
69*4882a593Smuzhiyun #define M_SYNCSER_TXSYNC_INT		   _SB_MAKEMASK1(15)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun  * Serial Command Register
73*4882a593Smuzhiyun  */
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define M_SYNCSER_CMD_RX_EN		   _SB_MAKEMASK1(0)
76*4882a593Smuzhiyun #define M_SYNCSER_CMD_TX_EN		   _SB_MAKEMASK1(1)
77*4882a593Smuzhiyun #define M_SYNCSER_CMD_RX_RESET		   _SB_MAKEMASK1(2)
78*4882a593Smuzhiyun #define M_SYNCSER_CMD_TX_RESET		   _SB_MAKEMASK1(3)
79*4882a593Smuzhiyun #define M_SYNCSER_CMD_TX_PAUSE		   _SB_MAKEMASK1(5)
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun  * Serial DMA Enable Register
83*4882a593Smuzhiyun  */
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define M_SYNCSER_DMA_RX_EN		   _SB_MAKEMASK1(0)
86*4882a593Smuzhiyun #define M_SYNCSER_DMA_TX_EN		   _SB_MAKEMASK1(4)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun  * Serial Status Register
90*4882a593Smuzhiyun  */
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define M_SYNCSER_RX_CRCERR		   _SB_MAKEMASK1(0)
93*4882a593Smuzhiyun #define M_SYNCSER_RX_ABORT		   _SB_MAKEMASK1(1)
94*4882a593Smuzhiyun #define M_SYNCSER_RX_OCTET		   _SB_MAKEMASK1(2)
95*4882a593Smuzhiyun #define M_SYNCSER_RX_LONGFRM		   _SB_MAKEMASK1(3)
96*4882a593Smuzhiyun #define M_SYNCSER_RX_SHORTFRM		   _SB_MAKEMASK1(4)
97*4882a593Smuzhiyun #define M_SYNCSER_RX_OVERRUN		   _SB_MAKEMASK1(5)
98*4882a593Smuzhiyun #define M_SYNCSER_RX_SYNC_ERR		   _SB_MAKEMASK1(6)
99*4882a593Smuzhiyun #define M_SYNCSER_TX_CRCERR		   _SB_MAKEMASK1(8)
100*4882a593Smuzhiyun #define M_SYNCSER_TX_UNDERRUN		   _SB_MAKEMASK1(9)
101*4882a593Smuzhiyun #define M_SYNCSER_TX_SYNC_ERR		   _SB_MAKEMASK1(10)
102*4882a593Smuzhiyun #define M_SYNCSER_TX_PAUSE_COMPLETE	   _SB_MAKEMASK1(11)
103*4882a593Smuzhiyun #define M_SYNCSER_RX_EOP_COUNT		   _SB_MAKEMASK1(16)
104*4882a593Smuzhiyun #define M_SYNCSER_RX_EOP_TIMER		   _SB_MAKEMASK1(17)
105*4882a593Smuzhiyun #define M_SYNCSER_RX_EOP_SEEN		   _SB_MAKEMASK1(18)
106*4882a593Smuzhiyun #define M_SYNCSER_RX_HWM		   _SB_MAKEMASK1(19)
107*4882a593Smuzhiyun #define M_SYNCSER_RX_LWM		   _SB_MAKEMASK1(20)
108*4882a593Smuzhiyun #define M_SYNCSER_RX_DSCR		   _SB_MAKEMASK1(21)
109*4882a593Smuzhiyun #define M_SYNCSER_RX_DERR		   _SB_MAKEMASK1(22)
110*4882a593Smuzhiyun #define M_SYNCSER_TX_EOP_COUNT		   _SB_MAKEMASK1(24)
111*4882a593Smuzhiyun #define M_SYNCSER_TX_EOP_TIMER		   _SB_MAKEMASK1(25)
112*4882a593Smuzhiyun #define M_SYNCSER_TX_EOP_SEEN		   _SB_MAKEMASK1(26)
113*4882a593Smuzhiyun #define M_SYNCSER_TX_HWM		   _SB_MAKEMASK1(27)
114*4882a593Smuzhiyun #define M_SYNCSER_TX_LWM		   _SB_MAKEMASK1(28)
115*4882a593Smuzhiyun #define M_SYNCSER_TX_DSCR		   _SB_MAKEMASK1(29)
116*4882a593Smuzhiyun #define M_SYNCSER_TX_DERR		   _SB_MAKEMASK1(30)
117*4882a593Smuzhiyun #define M_SYNCSER_TX_DZERO		   _SB_MAKEMASK1(31)
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun  * Sequencer Table Entry format
121*4882a593Smuzhiyun  */
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun #define M_SYNCSER_SEQ_LAST		   _SB_MAKEMASK1(0)
124*4882a593Smuzhiyun #define M_SYNCSER_SEQ_BYTE		   _SB_MAKEMASK1(1)
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun #define S_SYNCSER_SEQ_COUNT		   2
127*4882a593Smuzhiyun #define M_SYNCSER_SEQ_COUNT		   _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
128*4882a593Smuzhiyun #define V_SYNCSER_SEQ_COUNT(x)		   _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun #define M_SYNCSER_SEQ_ENABLE		   _SB_MAKEMASK1(6)
131*4882a593Smuzhiyun #define M_SYNCSER_SEQ_STROBE		   _SB_MAKEMASK1(7)
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #endif
134