xref: /OK3568_Linux_fs/kernel/arch/mips/include/asm/sibyte/sb1250_defs.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*  *********************************************************************
3*4882a593Smuzhiyun     *  SB1250 Board Support Package
4*4882a593Smuzhiyun     *
5*4882a593Smuzhiyun     *  Global constants and macros		File: sb1250_defs.h
6*4882a593Smuzhiyun     *
7*4882a593Smuzhiyun     *  This file contains macros and definitions used by the other
8*4882a593Smuzhiyun     *  include files.
9*4882a593Smuzhiyun     *
10*4882a593Smuzhiyun     *  SB1250 specification level:  User's manual 1/02/02
11*4882a593Smuzhiyun     *
12*4882a593Smuzhiyun     *********************************************************************
13*4882a593Smuzhiyun     *
14*4882a593Smuzhiyun     *  Copyright 2000,2001,2002,2003
15*4882a593Smuzhiyun     *  Broadcom Corporation. All rights reserved.
16*4882a593Smuzhiyun     *
17*4882a593Smuzhiyun     ********************************************************************* */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #ifndef _SB1250_DEFS_H
20*4882a593Smuzhiyun #define _SB1250_DEFS_H
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun  * These headers require ANSI C89 string concatenation, and GCC or other
24*4882a593Smuzhiyun  * 'long long' (64-bit integer) support.
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun #if !defined(__STDC__) && !defined(_MSC_VER)
27*4882a593Smuzhiyun #error SiByte headers require ANSI C89 support
28*4882a593Smuzhiyun #endif
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*  *********************************************************************
32*4882a593Smuzhiyun     *  Macros for feature tests, used to enable include file features
33*4882a593Smuzhiyun     *  for chip features only present in certain chip revisions.
34*4882a593Smuzhiyun     *
35*4882a593Smuzhiyun     *  SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
36*4882a593Smuzhiyun     *  which is to be exposed by the headers.  If undefined, it defaults to
37*4882a593Smuzhiyun     *  "all features."
38*4882a593Smuzhiyun     *
39*4882a593Smuzhiyun     *  Use like:
40*4882a593Smuzhiyun     *
41*4882a593Smuzhiyun     *	 #define SIBYTE_HDR_FEATURES	SIBYTE_HDR_FMASK_112x_PASS1
42*4882a593Smuzhiyun     *
43*4882a593Smuzhiyun     *		Generate defines only for that revision of chip.
44*4882a593Smuzhiyun     *
45*4882a593Smuzhiyun     *	 #if SIBYTE_HDR_FEATURE(chip,pass)
46*4882a593Smuzhiyun     *
47*4882a593Smuzhiyun     *		True if header features for that revision or later of
48*4882a593Smuzhiyun     *		that particular chip type are enabled in SIBYTE_HDR_FEATURES.
49*4882a593Smuzhiyun     *		(Use this to bracket #defines for features present in a given
50*4882a593Smuzhiyun     *		revision and later.)
51*4882a593Smuzhiyun     *
52*4882a593Smuzhiyun     *		Note that there is no implied ordering between chip types.
53*4882a593Smuzhiyun     *
54*4882a593Smuzhiyun     *		Note also that 'chip' and 'pass' must textually exactly
55*4882a593Smuzhiyun     *		match the defines below.  So, for example,
56*4882a593Smuzhiyun     *		SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
57*4882a593Smuzhiyun     *		SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
58*4882a593Smuzhiyun     *
59*4882a593Smuzhiyun     *	 #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
60*4882a593Smuzhiyun     *
61*4882a593Smuzhiyun     *		Same as SIBYTE_HDR_FEATURE, but true for the named revision
62*4882a593Smuzhiyun     *		and earlier revisions of the named chip type.
63*4882a593Smuzhiyun     *
64*4882a593Smuzhiyun     *	 #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
65*4882a593Smuzhiyun     *
66*4882a593Smuzhiyun     *		Same as SIBYTE_HDR_FEATURE, but only true for the named
67*4882a593Smuzhiyun     *		revision of the named chip type.  (Note that this CANNOT
68*4882a593Smuzhiyun     *		be used to verify that you're compiling only for that
69*4882a593Smuzhiyun     *		particular chip/revision.  It will be true any time this
70*4882a593Smuzhiyun     *		chip/revision is included in SIBYTE_HDR_FEATURES.)
71*4882a593Smuzhiyun     *
72*4882a593Smuzhiyun     *	 #if SIBYTE_HDR_FEATURE_CHIP(chip)
73*4882a593Smuzhiyun     *
74*4882a593Smuzhiyun     *		True if header features for (any revision of) that chip type
75*4882a593Smuzhiyun     *		are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket
76*4882a593Smuzhiyun     *		#defines for features specific to a given chip type.)
77*4882a593Smuzhiyun     *
78*4882a593Smuzhiyun     *  Mask values currently include room for additional revisions of each
79*4882a593Smuzhiyun     *  chip type, but can be renumbered at will.  Note that they MUST fit
80*4882a593Smuzhiyun     *  into 31 bits and may not include C type constructs, for safe use in
81*4882a593Smuzhiyun     *  CPP conditionals.  Bit positions within chip types DO indicate
82*4882a593Smuzhiyun     *  ordering, so be careful when adding support for new minor revs.
83*4882a593Smuzhiyun     ********************************************************************* */
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1250_ALL		0x000000ff
86*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1250_PASS1		0x00000001
87*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1250_PASS2		0x00000002
88*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1250_PASS3		0x00000004
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_112x_ALL		0x00000f00
91*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_112x_PASS1		0x00000100
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1480_ALL		0x0000f000
94*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1480_PASS1		0x00001000
95*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1480_PASS2		0x00002000
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* Bit mask for chip/revision.	(use _ALL for all revisions of a chip).	 */
98*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK(chip, pass)					\
99*4882a593Smuzhiyun     (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
100*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_ALLREVS(chip)					\
101*4882a593Smuzhiyun     (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* Default constant value for all chips, all revisions */
104*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_ALL						\
105*4882a593Smuzhiyun     (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL		\
106*4882a593Smuzhiyun      | SIBYTE_HDR_FMASK_1480_ALL)
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /* This one is used for the "original" BCM1250/BCM112x chips.  We use this
109*4882a593Smuzhiyun    to weed out constants and macros that do not exist on later chips like
110*4882a593Smuzhiyun    the BCM1480	*/
111*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1250_112x_ALL					\
112*4882a593Smuzhiyun     (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
113*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun #ifndef SIBYTE_HDR_FEATURES
116*4882a593Smuzhiyun #define SIBYTE_HDR_FEATURES			SIBYTE_HDR_FMASK_ALL
117*4882a593Smuzhiyun #endif
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /* Bit mask for revisions of chip exclusively before the named revision.  */
121*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_BEFORE(chip, pass)				\
122*4882a593Smuzhiyun     ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun /* Bit mask for revisions of chip exclusively after the named revision.	 */
125*4882a593Smuzhiyun #define SIBYTE_HDR_FMASK_AFTER(chip, pass)				\
126*4882a593Smuzhiyun     (~(SIBYTE_HDR_FMASK(chip, pass)					\
127*4882a593Smuzhiyun      | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /* True if header features enabled for (any revision of) that chip type.  */
131*4882a593Smuzhiyun #define SIBYTE_HDR_FEATURE_CHIP(chip)					\
132*4882a593Smuzhiyun     (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /* True for all versions of the BCM1250 and BCM1125, but not true for
135*4882a593Smuzhiyun    anything else */
136*4882a593Smuzhiyun #define SIBYTE_HDR_FEATURE_1250_112x \
137*4882a593Smuzhiyun       (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
138*4882a593Smuzhiyun /*    (!!  (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* True if header features enabled for that rev or later, inclusive.  */
141*4882a593Smuzhiyun #define SIBYTE_HDR_FEATURE(chip, pass)					\
142*4882a593Smuzhiyun     (!! ((SIBYTE_HDR_FMASK(chip, pass)					\
143*4882a593Smuzhiyun 	  | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /* True if header features enabled for exactly that rev.  */
146*4882a593Smuzhiyun #define SIBYTE_HDR_FEATURE_EXACT(chip, pass)				\
147*4882a593Smuzhiyun     (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun /* True if header features enabled for that rev or before, inclusive.  */
150*4882a593Smuzhiyun #define SIBYTE_HDR_FEATURE_UP_TO(chip, pass)				\
151*4882a593Smuzhiyun     (!! ((SIBYTE_HDR_FMASK(chip, pass)					\
152*4882a593Smuzhiyun 	 | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun /*  *********************************************************************
156*4882a593Smuzhiyun     *  Naming schemes for constants in these files:
157*4882a593Smuzhiyun     *
158*4882a593Smuzhiyun     *  M_xxx	       MASK constant (identifies bits in a register).
159*4882a593Smuzhiyun     *		       For multi-bit fields, all bits in the field will
160*4882a593Smuzhiyun     *		       be set.
161*4882a593Smuzhiyun     *
162*4882a593Smuzhiyun     *  K_xxx	       "Code" constant (value for data in a multi-bit
163*4882a593Smuzhiyun     *		       field).	The value is right justified.
164*4882a593Smuzhiyun     *
165*4882a593Smuzhiyun     *  V_xxx	       "Value" constant.  This is the same as the
166*4882a593Smuzhiyun     *		       corresponding "K_xxx" constant, except it is
167*4882a593Smuzhiyun     *		       shifted to the correct position in the register.
168*4882a593Smuzhiyun     *
169*4882a593Smuzhiyun     *  S_xxx	       SHIFT constant.	This is the number of bits that
170*4882a593Smuzhiyun     *		       a field value (code) needs to be shifted
171*4882a593Smuzhiyun     *		       (towards the left) to put the value in the right
172*4882a593Smuzhiyun     *		       position for the register.
173*4882a593Smuzhiyun     *
174*4882a593Smuzhiyun     *  A_xxx	       ADDRESS constant.  This will be a physical
175*4882a593Smuzhiyun     *		       address.	 Use the PHYS_TO_K1 macro to generate
176*4882a593Smuzhiyun     *		       a K1SEG address.
177*4882a593Smuzhiyun     *
178*4882a593Smuzhiyun     *  R_xxx	       RELATIVE offset constant.  This is an offset from
179*4882a593Smuzhiyun     *		       an A_xxx constant (usually the first register in
180*4882a593Smuzhiyun     *		       a group).
181*4882a593Smuzhiyun     *
182*4882a593Smuzhiyun     *  G_xxx(X)	       GET value.  This macro obtains a multi-bit field
183*4882a593Smuzhiyun     *		       from a register, masks it, and shifts it to
184*4882a593Smuzhiyun     *		       the bottom of the register (retrieving a K_xxx
185*4882a593Smuzhiyun     *		       value, for example).
186*4882a593Smuzhiyun     *
187*4882a593Smuzhiyun     *  V_xxx(X)	       VALUE.  This macro computes the value of a
188*4882a593Smuzhiyun     *		       K_xxx constant shifted to the correct position
189*4882a593Smuzhiyun     *		       in the register.
190*4882a593Smuzhiyun     ********************************************************************* */
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /*
196*4882a593Smuzhiyun  * Cast to 64-bit number.  Presumably the syntax is different in
197*4882a593Smuzhiyun  * assembly language.
198*4882a593Smuzhiyun  *
199*4882a593Smuzhiyun  * Note: you'll need to define uint32_t and uint64_t in your headers.
200*4882a593Smuzhiyun  */
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun #if !defined(__ASSEMBLY__)
203*4882a593Smuzhiyun #define _SB_MAKE64(x) ((uint64_t)(x))
204*4882a593Smuzhiyun #define _SB_MAKE32(x) ((uint32_t)(x))
205*4882a593Smuzhiyun #else
206*4882a593Smuzhiyun #define _SB_MAKE64(x) (x)
207*4882a593Smuzhiyun #define _SB_MAKE32(x) (x)
208*4882a593Smuzhiyun #endif
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /*
212*4882a593Smuzhiyun  * Make a mask for 1 bit at position 'n'
213*4882a593Smuzhiyun  */
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun #define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
216*4882a593Smuzhiyun #define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun /*
219*4882a593Smuzhiyun  * Make a mask for 'v' bits at position 'n'
220*4882a593Smuzhiyun  */
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun #define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
223*4882a593Smuzhiyun #define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun /*
226*4882a593Smuzhiyun  * Make a value at 'v' at bit position 'n'
227*4882a593Smuzhiyun  */
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun #define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
230*4882a593Smuzhiyun #define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun #define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
233*4882a593Smuzhiyun #define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun /*
236*4882a593Smuzhiyun  * Macros to read/write on-chip registers
237*4882a593Smuzhiyun  * XXX should we do the PHYS_TO_K1 here?
238*4882a593Smuzhiyun  */
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun #if defined(__mips64) && !defined(__ASSEMBLY__)
242*4882a593Smuzhiyun #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
243*4882a593Smuzhiyun #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
244*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun #endif
247