1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2002 Broadcom Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __ASM_SIBYTE_CARMEL_H 6*4882a593Smuzhiyun #define __ASM_SIBYTE_CARMEL_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <asm/sibyte/sb1250.h> 9*4882a593Smuzhiyun #include <asm/sibyte/sb1250_int.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SIBYTE_BOARD_NAME "Carmel" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define GPIO_PHY_INTERRUPT 2 14*4882a593Smuzhiyun #define GPIO_NONMASKABLE_INT 3 15*4882a593Smuzhiyun #define GPIO_CF_INSERTED 6 16*4882a593Smuzhiyun #define GPIO_MONTEREY_RESET 7 17*4882a593Smuzhiyun #define GPIO_QUADUART_INT 8 18*4882a593Smuzhiyun #define GPIO_CF_INT 9 19*4882a593Smuzhiyun #define GPIO_FPGA_CCLK 10 20*4882a593Smuzhiyun #define GPIO_FPGA_DOUT 11 21*4882a593Smuzhiyun #define GPIO_FPGA_DIN 12 22*4882a593Smuzhiyun #define GPIO_FPGA_PGM 13 23*4882a593Smuzhiyun #define GPIO_FPGA_DONE 14 24*4882a593Smuzhiyun #define GPIO_FPGA_INIT 15 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define LEDS_CS 2 27*4882a593Smuzhiyun #define LEDS_PHYS 0x100C0000 28*4882a593Smuzhiyun #define MLEDS_CS 3 29*4882a593Smuzhiyun #define MLEDS_PHYS 0x100A0000 30*4882a593Smuzhiyun #define UART_CS 4 31*4882a593Smuzhiyun #define UART_PHYS 0x100D0000 32*4882a593Smuzhiyun #define ARAVALI_CS 5 33*4882a593Smuzhiyun #define ARAVALI_PHYS 0x11000000 34*4882a593Smuzhiyun #define IDE_CS 6 35*4882a593Smuzhiyun #define IDE_PHYS 0x100B0000 36*4882a593Smuzhiyun #define ARAVALI2_CS 7 37*4882a593Smuzhiyun #define ARAVALI2_PHYS 0x100E0000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #if defined(CONFIG_SIBYTE_CARMEL) 40*4882a593Smuzhiyun #define K_GPIO_GB_IDE 9 41*4882a593Smuzhiyun #define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /* __ASM_SIBYTE_CARMEL_H */ 46