1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * ioc.h: Definitions for SGI I/O Controller 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 1996 David S. Miller 9*4882a593Smuzhiyun * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle 10*4882a593Smuzhiyun * Copyright (C) 2001, 2003 Ladislav Michl 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _SGI_IOC_H 14*4882a593Smuzhiyun #define _SGI_IOC_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <linux/types.h> 17*4882a593Smuzhiyun #include <asm/sgi/pi1.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * All registers are 8-bit wide aligned on 32-bit boundary. Bad things 21*4882a593Smuzhiyun * happen if you try word access them. You have been warned. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct sgioc_uart_regs { 25*4882a593Smuzhiyun u8 _ctrl1[3]; 26*4882a593Smuzhiyun volatile u8 ctrl1; 27*4882a593Smuzhiyun u8 _data1[3]; 28*4882a593Smuzhiyun volatile u8 data1; 29*4882a593Smuzhiyun u8 _ctrl2[3]; 30*4882a593Smuzhiyun volatile u8 ctrl2; 31*4882a593Smuzhiyun u8 _data2[3]; 32*4882a593Smuzhiyun volatile u8 data2; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct sgioc_keyb_regs { 36*4882a593Smuzhiyun u8 _data[3]; 37*4882a593Smuzhiyun volatile u8 data; 38*4882a593Smuzhiyun u8 _command[3]; 39*4882a593Smuzhiyun volatile u8 command; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct sgint_regs { 43*4882a593Smuzhiyun u8 _istat0[3]; 44*4882a593Smuzhiyun volatile u8 istat0; /* Interrupt status zero */ 45*4882a593Smuzhiyun #define SGINT_ISTAT0_FFULL 0x01 46*4882a593Smuzhiyun #define SGINT_ISTAT0_SCSI0 0x02 47*4882a593Smuzhiyun #define SGINT_ISTAT0_SCSI1 0x04 48*4882a593Smuzhiyun #define SGINT_ISTAT0_ENET 0x08 49*4882a593Smuzhiyun #define SGINT_ISTAT0_GFXDMA 0x10 50*4882a593Smuzhiyun #define SGINT_ISTAT0_PPORT 0x20 51*4882a593Smuzhiyun #define SGINT_ISTAT0_HPC2 0x40 52*4882a593Smuzhiyun #define SGINT_ISTAT0_LIO2 0x80 53*4882a593Smuzhiyun u8 _imask0[3]; 54*4882a593Smuzhiyun volatile u8 imask0; /* Interrupt mask zero */ 55*4882a593Smuzhiyun u8 _istat1[3]; 56*4882a593Smuzhiyun volatile u8 istat1; /* Interrupt status one */ 57*4882a593Smuzhiyun #define SGINT_ISTAT1_ISDNI 0x01 58*4882a593Smuzhiyun #define SGINT_ISTAT1_PWR 0x02 59*4882a593Smuzhiyun #define SGINT_ISTAT1_ISDNH 0x04 60*4882a593Smuzhiyun #define SGINT_ISTAT1_LIO3 0x08 61*4882a593Smuzhiyun #define SGINT_ISTAT1_HPC3 0x10 62*4882a593Smuzhiyun #define SGINT_ISTAT1_AFAIL 0x20 63*4882a593Smuzhiyun #define SGINT_ISTAT1_VIDEO 0x40 64*4882a593Smuzhiyun #define SGINT_ISTAT1_GIO2 0x80 65*4882a593Smuzhiyun u8 _imask1[3]; 66*4882a593Smuzhiyun volatile u8 imask1; /* Interrupt mask one */ 67*4882a593Smuzhiyun u8 _vmeistat[3]; 68*4882a593Smuzhiyun volatile u8 vmeistat; /* VME interrupt status */ 69*4882a593Smuzhiyun u8 _cmeimask0[3]; 70*4882a593Smuzhiyun volatile u8 cmeimask0; /* VME interrupt mask zero */ 71*4882a593Smuzhiyun u8 _cmeimask1[3]; 72*4882a593Smuzhiyun volatile u8 cmeimask1; /* VME interrupt mask one */ 73*4882a593Smuzhiyun u8 _cmepol[3]; 74*4882a593Smuzhiyun volatile u8 cmepol; /* VME polarity */ 75*4882a593Smuzhiyun u8 _tclear[3]; 76*4882a593Smuzhiyun volatile u8 tclear; 77*4882a593Smuzhiyun u8 _errstat[3]; 78*4882a593Smuzhiyun volatile u8 errstat; /* Error status reg, reserved on INT2 */ 79*4882a593Smuzhiyun u32 _unused0[2]; 80*4882a593Smuzhiyun u8 _tcnt0[3]; 81*4882a593Smuzhiyun volatile u8 tcnt0; /* counter 0 */ 82*4882a593Smuzhiyun u8 _tcnt1[3]; 83*4882a593Smuzhiyun volatile u8 tcnt1; /* counter 1 */ 84*4882a593Smuzhiyun u8 _tcnt2[3]; 85*4882a593Smuzhiyun volatile u8 tcnt2; /* counter 2 */ 86*4882a593Smuzhiyun u8 _tcword[3]; 87*4882a593Smuzhiyun volatile u8 tcword; /* control word */ 88*4882a593Smuzhiyun #define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ 89*4882a593Smuzhiyun #define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ 90*4882a593Smuzhiyun #define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */ 91*4882a593Smuzhiyun #define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */ 92*4882a593Smuzhiyun #define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */ 93*4882a593Smuzhiyun #define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */ 94*4882a593Smuzhiyun #define SGINT_TCWORD_MSWST 0x08 /* Software strobe */ 95*4882a593Smuzhiyun #define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */ 96*4882a593Smuzhiyun #define SGINT_TCWORD_CMASK 0x30 /* Command mask */ 97*4882a593Smuzhiyun #define SGINT_TCWORD_CLAT 0x00 /* Latch command */ 98*4882a593Smuzhiyun #define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */ 99*4882a593Smuzhiyun #define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */ 100*4882a593Smuzhiyun #define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */ 101*4882a593Smuzhiyun #define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */ 102*4882a593Smuzhiyun #define SGINT_TCWORD_CNT1 0x40 /* Select counter one */ 103*4882a593Smuzhiyun #define SGINT_TCWORD_CNT2 0x80 /* Select counter two */ 104*4882a593Smuzhiyun #define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */ 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* 108*4882a593Smuzhiyun * The timer is the good old 8254. Unlike in PCs it's clocked at exactly 1MHz 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun #define SGINT_TIMER_CLOCK 1000000 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * This is the constant we're using for calibrating the counter. 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun #define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* We need software copies of these because they are write only. */ 118*4882a593Smuzhiyun extern u8 sgi_ioc_reset, sgi_ioc_write; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct sgioc_regs { 121*4882a593Smuzhiyun struct pi1_regs pport; 122*4882a593Smuzhiyun u32 _unused0[2]; 123*4882a593Smuzhiyun struct sgioc_uart_regs uart; 124*4882a593Smuzhiyun struct sgioc_keyb_regs kbdmouse; 125*4882a593Smuzhiyun u8 _gcsel[3]; 126*4882a593Smuzhiyun volatile u8 gcsel; 127*4882a593Smuzhiyun u8 _genctrl[3]; 128*4882a593Smuzhiyun volatile u8 genctrl; 129*4882a593Smuzhiyun u8 _panel[3]; 130*4882a593Smuzhiyun volatile u8 panel; 131*4882a593Smuzhiyun #define SGIOC_PANEL_POWERON 0x01 132*4882a593Smuzhiyun #define SGIOC_PANEL_POWERINTR 0x02 133*4882a593Smuzhiyun #define SGIOC_PANEL_VOLDNINTR 0x10 134*4882a593Smuzhiyun #define SGIOC_PANEL_VOLDNHOLD 0x20 135*4882a593Smuzhiyun #define SGIOC_PANEL_VOLUPINTR 0x40 136*4882a593Smuzhiyun #define SGIOC_PANEL_VOLUPHOLD 0x80 137*4882a593Smuzhiyun u32 _unused1; 138*4882a593Smuzhiyun u8 _sysid[3]; 139*4882a593Smuzhiyun volatile u8 sysid; 140*4882a593Smuzhiyun #define SGIOC_SYSID_FULLHOUSE 0x01 141*4882a593Smuzhiyun #define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1) 142*4882a593Smuzhiyun #define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5) 143*4882a593Smuzhiyun u32 _unused2; 144*4882a593Smuzhiyun u8 _read[3]; 145*4882a593Smuzhiyun volatile u8 read; 146*4882a593Smuzhiyun u32 _unused3; 147*4882a593Smuzhiyun u8 _dmasel[3]; 148*4882a593Smuzhiyun volatile u8 dmasel; 149*4882a593Smuzhiyun #define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ 150*4882a593Smuzhiyun #define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */ 151*4882a593Smuzhiyun #define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */ 152*4882a593Smuzhiyun #define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */ 153*4882a593Smuzhiyun #define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ 154*4882a593Smuzhiyun #define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */ 155*4882a593Smuzhiyun u32 _unused4; 156*4882a593Smuzhiyun u8 _reset[3]; 157*4882a593Smuzhiyun volatile u8 reset; 158*4882a593Smuzhiyun #define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */ 159*4882a593Smuzhiyun #define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */ 160*4882a593Smuzhiyun #define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */ 161*4882a593Smuzhiyun #define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */ 162*4882a593Smuzhiyun #define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */ 163*4882a593Smuzhiyun #define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */ 164*4882a593Smuzhiyun u32 _unused5; 165*4882a593Smuzhiyun u8 _write[3]; 166*4882a593Smuzhiyun volatile u8 write; 167*4882a593Smuzhiyun #define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshold */ 168*4882a593Smuzhiyun #define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ 169*4882a593Smuzhiyun #define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ 170*4882a593Smuzhiyun #define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ 171*4882a593Smuzhiyun #define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */ 172*4882a593Smuzhiyun #define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */ 173*4882a593Smuzhiyun #define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */ 174*4882a593Smuzhiyun #define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */ 175*4882a593Smuzhiyun u32 _unused6; 176*4882a593Smuzhiyun struct sgint_regs int3; 177*4882a593Smuzhiyun u32 _unused7[16]; 178*4882a593Smuzhiyun volatile u32 extio; /* FullHouse only */ 179*4882a593Smuzhiyun #define EXTIO_S0_IRQ_3 0x8000 /* S0: vid.vsync */ 180*4882a593Smuzhiyun #define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */ 181*4882a593Smuzhiyun #define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */ 182*4882a593Smuzhiyun #define EXTIO_S0_RETRACE 0x1000 183*4882a593Smuzhiyun #define EXTIO_SG_IRQ_3 0x0800 /* SG: vid.vsync */ 184*4882a593Smuzhiyun #define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */ 185*4882a593Smuzhiyun #define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */ 186*4882a593Smuzhiyun #define EXTIO_SG_RETRACE 0x0100 187*4882a593Smuzhiyun #define EXTIO_GIO_33MHZ 0x0080 188*4882a593Smuzhiyun #define EXTIO_EISA_BUSERR 0x0040 189*4882a593Smuzhiyun #define EXTIO_MC_BUSERR 0x0020 190*4882a593Smuzhiyun #define EXTIO_HPC3_BUSERR 0x0010 191*4882a593Smuzhiyun #define EXTIO_S0_STAT_1 0x0008 192*4882a593Smuzhiyun #define EXTIO_S0_STAT_0 0x0004 193*4882a593Smuzhiyun #define EXTIO_SG_STAT_1 0x0002 194*4882a593Smuzhiyun #define EXTIO_SG_STAT_0 0x0001 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun extern struct sgioc_regs *sgioc; 198*4882a593Smuzhiyun extern struct sgint_regs *sgint; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #endif 201