1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2003 by Ralf Baechle 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __ASM_PREFETCH_H 9*4882a593Smuzhiyun #define __ASM_PREFETCH_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * R5000 and RM5200 implements pref and prefx instructions but they're nops, so 14*4882a593Smuzhiyun * rather than wasting time we pretend these processors don't support 15*4882a593Smuzhiyun * prefetching at all. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained, 18*4882a593Smuzhiyun * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * Hell (and the book on my shelf I can't open ...) know what the R8000 does. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements 23*4882a593Smuzhiyun * Pref_PrepareForStore also. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's 26*4882a593Smuzhiyun * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in 27*4882a593Smuzhiyun * current versions due to erratum G105. 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * VR5500 (including VR5701 and VR7701) only implement load prefetch. 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * Finally MIPS32 and MIPS64 implement all of the following hints. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define Pref_Load 0 35*4882a593Smuzhiyun #define Pref_Store 1 36*4882a593Smuzhiyun /* 2 and 3 are reserved */ 37*4882a593Smuzhiyun #define Pref_LoadStreamed 4 38*4882a593Smuzhiyun #define Pref_StoreStreamed 5 39*4882a593Smuzhiyun #define Pref_LoadRetained 6 40*4882a593Smuzhiyun #define Pref_StoreRetained 7 41*4882a593Smuzhiyun /* 8 ... 24 are reserved */ 42*4882a593Smuzhiyun #define Pref_WriteBackInvalidate 25 43*4882a593Smuzhiyun #define Pref_PrepareForStore 30 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #ifdef __ASSEMBLY__ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun .macro __pref hint addr 48*4882a593Smuzhiyun #ifdef CONFIG_CPU_HAS_PREFETCH 49*4882a593Smuzhiyun pref \hint, \addr 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun .endm 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun .macro pref_load addr 54*4882a593Smuzhiyun __pref Pref_Load, \addr 55*4882a593Smuzhiyun .endm 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun .macro pref_store addr 58*4882a593Smuzhiyun __pref Pref_Store, \addr 59*4882a593Smuzhiyun .endm 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun .macro pref_load_streamed addr 62*4882a593Smuzhiyun __pref Pref_LoadStreamed, \addr 63*4882a593Smuzhiyun .endm 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun .macro pref_store_streamed addr 66*4882a593Smuzhiyun __pref Pref_StoreStreamed, \addr 67*4882a593Smuzhiyun .endm 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun .macro pref_load_retained addr 70*4882a593Smuzhiyun __pref Pref_LoadRetained, \addr 71*4882a593Smuzhiyun .endm 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun .macro pref_store_retained addr 74*4882a593Smuzhiyun __pref Pref_StoreRetained, \addr 75*4882a593Smuzhiyun .endm 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun .macro pref_wback_inv addr 78*4882a593Smuzhiyun __pref Pref_WriteBackInvalidate, \addr 79*4882a593Smuzhiyun .endm 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun .macro pref_prepare_for_store addr 82*4882a593Smuzhiyun __pref Pref_PrepareForStore, \addr 83*4882a593Smuzhiyun .endm 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* __ASM_PREFETCH_H */ 88