1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Imagination Technologies 4*4882a593Smuzhiyun * Author: Paul Burton <paul.burton@mips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MIPS_ASM_PM_CPS_H__ 8*4882a593Smuzhiyun #define __MIPS_ASM_PM_CPS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * The CM & CPC can only handle coherence & power control on a per-core basis, 12*4882a593Smuzhiyun * thus in an MT system the VP(E)s within each core are coupled and can only 13*4882a593Smuzhiyun * enter or exit states requiring CM or CPC assistance in unison. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #if defined(CONFIG_CPU_MIPSR6) 16*4882a593Smuzhiyun # define coupled_coherence cpu_has_vp 17*4882a593Smuzhiyun #elif defined(CONFIG_MIPS_MT) 18*4882a593Smuzhiyun # define coupled_coherence cpu_has_mipsmt 19*4882a593Smuzhiyun #else 20*4882a593Smuzhiyun # define coupled_coherence 0 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Enumeration of possible PM states */ 24*4882a593Smuzhiyun enum cps_pm_state { 25*4882a593Smuzhiyun CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */ 26*4882a593Smuzhiyun CPS_PM_CLOCK_GATED, /* Core clock gated */ 27*4882a593Smuzhiyun CPS_PM_POWER_GATED, /* Core power gated */ 28*4882a593Smuzhiyun CPS_PM_STATE_COUNT, 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /** 32*4882a593Smuzhiyun * cps_pm_support_state - determine whether the system supports a PM state 33*4882a593Smuzhiyun * @state: the state to test for support 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * Returns true if the system supports the given state, otherwise false. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun extern bool cps_pm_support_state(enum cps_pm_state state); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /** 40*4882a593Smuzhiyun * cps_pm_enter_state - enter a PM state 41*4882a593Smuzhiyun * @state: the state to enter 42*4882a593Smuzhiyun * 43*4882a593Smuzhiyun * Enter the given PM state. If coupled_coherence is non-zero then it is 44*4882a593Smuzhiyun * expected that this function be called at approximately the same time on 45*4882a593Smuzhiyun * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun extern int cps_pm_enter_state(enum cps_pm_state state); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif /* __MIPS_ASM_PM_CPS_H__ */ 50