1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2005-2009 Cavium Networks 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __PCI_OCTEON_H__ 10*4882a593Smuzhiyun #define __PCI_OCTEON_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/pci.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * The physical memory base mapped by BAR1. 256MB at the end of the 16*4882a593Smuzhiyun * first 4GB. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28)) 19*4882a593Smuzhiyun #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, 23*4882a593Smuzhiyun * place BAR1 so it is the same for both. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * pcibios_map_irq() is defined inside pci-octeon.c. All it does is 29*4882a593Smuzhiyun * call the Octeon specific version pointed to by this variable. This 30*4882a593Smuzhiyun * function needs to change for PCI or PCIe based hosts. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, 33*4882a593Smuzhiyun u8 slot, u8 pin); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * For PCI (not PCIe) the BAR2 base address. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * For PCI (not PCIe) the base of the memory mapped by BAR1 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun extern u64 octeon_bar1_pci_phys; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * The following defines are used when octeon_dma_bar_type = 47*4882a593Smuzhiyun * OCTEON_DMA_BAR_TYPE_BIG 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define OCTEON_PCI_BAR1_HOLE_BITS 5 50*4882a593Smuzhiyun #define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3)) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun enum octeon_dma_bar_type { 53*4882a593Smuzhiyun OCTEON_DMA_BAR_TYPE_INVALID, 54*4882a593Smuzhiyun OCTEON_DMA_BAR_TYPE_SMALL, 55*4882a593Smuzhiyun OCTEON_DMA_BAR_TYPE_BIG, 56*4882a593Smuzhiyun OCTEON_DMA_BAR_TYPE_PCIE, 57*4882a593Smuzhiyun OCTEON_DMA_BAR_TYPE_PCIE2 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * This tells the DMA mapping system in dma-octeon.c how to map PCI 62*4882a593Smuzhiyun * DMA addresses. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun extern enum octeon_dma_bar_type octeon_dma_bar_type; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun void octeon_pci_dma_init(void); 67*4882a593Smuzhiyun extern char *octeon_swiotlb; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70