xref: /OK3568_Linux_fs/kernel/arch/mips/include/asm/octeon/cvmx-sli-defs.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /***********************license start***************
2*4882a593Smuzhiyun  * Author: Cavium Networks
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Contact: support@caviumnetworks.com
5*4882a593Smuzhiyun  * This file is part of the OCTEON SDK
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (c) 2003-2017 Cavium, Inc.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This file is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun  * it under the terms of the GNU General Public License, Version 2, as
11*4882a593Smuzhiyun  * published by the Free Software Foundation.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This file is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16*4882a593Smuzhiyun  * NONINFRINGEMENT.  See the GNU General Public License for more
17*4882a593Smuzhiyun  * details.
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  * You should have received a copy of the GNU General Public License
20*4882a593Smuzhiyun  * along with this file; if not, write to the Free Software
21*4882a593Smuzhiyun  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22*4882a593Smuzhiyun  * or visit http://www.gnu.org/licenses/.
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  * This file may also be available under a different license from Cavium.
25*4882a593Smuzhiyun  * Contact Cavium Networks for more information
26*4882a593Smuzhiyun  ***********************license end**************************************/
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #ifndef __CVMX_SLI_DEFS_H__
29*4882a593Smuzhiyun #define __CVMX_SLI_DEFS_H__
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <uapi/asm/bitfield.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
CVMX_SLI_PCIE_MSI_RCV_FUNC(void)34*4882a593Smuzhiyun static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	switch (cvmx_get_octeon_family()) {
37*4882a593Smuzhiyun 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
38*4882a593Smuzhiyun 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
39*4882a593Smuzhiyun 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40*4882a593Smuzhiyun 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41*4882a593Smuzhiyun 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42*4882a593Smuzhiyun 	case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
43*4882a593Smuzhiyun 		return 0x0000000000003CB0ull;
44*4882a593Smuzhiyun 	case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
45*4882a593Smuzhiyun 	case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
46*4882a593Smuzhiyun 	case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
47*4882a593Smuzhiyun 		if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
48*4882a593Smuzhiyun 			return 0x0000000000003CB0ull;
49*4882a593Smuzhiyun 		fallthrough;
50*4882a593Smuzhiyun 	default:
51*4882a593Smuzhiyun 		return 0x0000000000023CB0ull;
52*4882a593Smuzhiyun 	}
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun union cvmx_sli_ctl_portx {
57*4882a593Smuzhiyun 	uint64_t u64;
58*4882a593Smuzhiyun 	struct cvmx_sli_ctl_portx_s {
59*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_22_63:42,
60*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t intd:1,
61*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t intc:1,
62*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t intb:1,
63*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t inta:1,
64*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t dis_port:1,
65*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t waitl_com:1,
66*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t intd_map:2,
67*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t intc_map:2,
68*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t intb_map:2,
69*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t inta_map:2,
70*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t ctlp_ro:1,
71*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_6_6:1,
72*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t ptlp_ro:1,
73*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_1_4:4,
74*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t wait_com:1,
75*4882a593Smuzhiyun 		;))))))))))))))))
76*4882a593Smuzhiyun 	} s;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun union cvmx_sli_mem_access_ctl {
80*4882a593Smuzhiyun 	uint64_t u64;
81*4882a593Smuzhiyun 	struct cvmx_sli_mem_access_ctl_s {
82*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_14_63:50,
83*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t max_word:4,
84*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t timer:10,
85*4882a593Smuzhiyun 		;)))
86*4882a593Smuzhiyun 	} s;
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun union cvmx_sli_s2m_portx_ctl {
90*4882a593Smuzhiyun 	uint64_t u64;
91*4882a593Smuzhiyun 	struct cvmx_sli_s2m_portx_ctl_s {
92*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_5_63:59,
93*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t wind_d:1,
94*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t bar0_d:1,
95*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t mrrs:3,
96*4882a593Smuzhiyun 		;))))
97*4882a593Smuzhiyun 	} s;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun union cvmx_sli_mem_access_subidx {
101*4882a593Smuzhiyun 	uint64_t u64;
102*4882a593Smuzhiyun 	struct cvmx_sli_mem_access_subidx_s {
103*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_43_63:21,
104*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t zero:1,
105*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t port:3,
106*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t nmerge:1,
107*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t esr:2,
108*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t esw:2,
109*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t wtype:2,
110*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t rtype:2,
111*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t ba:30,
112*4882a593Smuzhiyun 		;)))))))))
113*4882a593Smuzhiyun 	} s;
114*4882a593Smuzhiyun 	struct cvmx_sli_mem_access_subidx_cn68xx {
115*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_43_63:21,
116*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t zero:1,
117*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t port:3,
118*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t nmerge:1,
119*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t esr:2,
120*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t esw:2,
121*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t wtype:2,
122*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t rtype:2,
123*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t ba:28,
124*4882a593Smuzhiyun 		__BITFIELD_FIELD(uint64_t reserved_0_1:2,
125*4882a593Smuzhiyun 		;))))))))))
126*4882a593Smuzhiyun 	} cn68xx;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #endif
130