xref: /OK3568_Linux_fs/kernel/arch/mips/include/asm/octeon/cvmx-fpa.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /***********************license start***************
2*4882a593Smuzhiyun  * Author: Cavium Networks
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Contact: support@caviumnetworks.com
5*4882a593Smuzhiyun  * This file is part of the OCTEON SDK
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (c) 2003-2008 Cavium Networks
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This file is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun  * it under the terms of the GNU General Public License, Version 2, as
11*4882a593Smuzhiyun  * published by the Free Software Foundation.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This file is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16*4882a593Smuzhiyun  * NONINFRINGEMENT.  See the GNU General Public License for more
17*4882a593Smuzhiyun  * details.
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  * You should have received a copy of the GNU General Public License
20*4882a593Smuzhiyun  * along with this file; if not, write to the Free Software
21*4882a593Smuzhiyun  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22*4882a593Smuzhiyun  * or visit http://www.gnu.org/licenses/.
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  * This file may also be available under a different license from Cavium.
25*4882a593Smuzhiyun  * Contact Cavium Networks for more information
26*4882a593Smuzhiyun  ***********************license end**************************************/
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /**
29*4882a593Smuzhiyun  * @file
30*4882a593Smuzhiyun  *
31*4882a593Smuzhiyun  * Interface to the hardware Free Pool Allocator.
32*4882a593Smuzhiyun  *
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  */
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #ifndef __CVMX_FPA_H__
37*4882a593Smuzhiyun #define __CVMX_FPA_H__
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include <linux/delay.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #include <asm/octeon/cvmx-address.h>
42*4882a593Smuzhiyun #include <asm/octeon/cvmx-fpa-defs.h>
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define CVMX_FPA_NUM_POOLS	8
45*4882a593Smuzhiyun #define CVMX_FPA_MIN_BLOCK_SIZE 128
46*4882a593Smuzhiyun #define CVMX_FPA_ALIGNMENT	128
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun  * Structure describing the data format used for stores to the FPA.
50*4882a593Smuzhiyun  */
51*4882a593Smuzhiyun typedef union {
52*4882a593Smuzhiyun 	uint64_t u64;
53*4882a593Smuzhiyun 	struct {
54*4882a593Smuzhiyun #ifdef __BIG_ENDIAN_BITFIELD
55*4882a593Smuzhiyun 		/*
56*4882a593Smuzhiyun 		 * the (64-bit word) location in scratchpad to write
57*4882a593Smuzhiyun 		 * to (if len != 0)
58*4882a593Smuzhiyun 		 */
59*4882a593Smuzhiyun 		uint64_t scraddr:8;
60*4882a593Smuzhiyun 		/* the number of words in the response (0 => no response) */
61*4882a593Smuzhiyun 		uint64_t len:8;
62*4882a593Smuzhiyun 		/* the ID of the device on the non-coherent bus */
63*4882a593Smuzhiyun 		uint64_t did:8;
64*4882a593Smuzhiyun 		/*
65*4882a593Smuzhiyun 		 * the address that will appear in the first tick on
66*4882a593Smuzhiyun 		 * the NCB bus.
67*4882a593Smuzhiyun 		 */
68*4882a593Smuzhiyun 		uint64_t addr:40;
69*4882a593Smuzhiyun #else
70*4882a593Smuzhiyun 		uint64_t addr:40;
71*4882a593Smuzhiyun 		uint64_t did:8;
72*4882a593Smuzhiyun 		uint64_t len:8;
73*4882a593Smuzhiyun 		uint64_t scraddr:8;
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun 	} s;
76*4882a593Smuzhiyun } cvmx_fpa_iobdma_data_t;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /**
79*4882a593Smuzhiyun  * Structure describing the current state of a FPA pool.
80*4882a593Smuzhiyun  */
81*4882a593Smuzhiyun typedef struct {
82*4882a593Smuzhiyun 	/* Name it was created under */
83*4882a593Smuzhiyun 	const char *name;
84*4882a593Smuzhiyun 	/* Size of each block */
85*4882a593Smuzhiyun 	uint64_t size;
86*4882a593Smuzhiyun 	/* The base memory address of whole block */
87*4882a593Smuzhiyun 	void *base;
88*4882a593Smuzhiyun 	/* The number of elements in the pool at creation */
89*4882a593Smuzhiyun 	uint64_t starting_element_count;
90*4882a593Smuzhiyun } cvmx_fpa_pool_info_t;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /**
93*4882a593Smuzhiyun  * Current state of all the pools. Use access functions
94*4882a593Smuzhiyun  * instead of using it directly.
95*4882a593Smuzhiyun  */
96*4882a593Smuzhiyun extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /* CSR typedefs have been moved to cvmx-csr-*.h */
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /**
101*4882a593Smuzhiyun  * Return the name of the pool
102*4882a593Smuzhiyun  *
103*4882a593Smuzhiyun  * @pool:   Pool to get the name of
104*4882a593Smuzhiyun  * Returns The name
105*4882a593Smuzhiyun  */
cvmx_fpa_get_name(uint64_t pool)106*4882a593Smuzhiyun static inline const char *cvmx_fpa_get_name(uint64_t pool)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	return cvmx_fpa_pool_info[pool].name;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /**
112*4882a593Smuzhiyun  * Return the base of the pool
113*4882a593Smuzhiyun  *
114*4882a593Smuzhiyun  * @pool:   Pool to get the base of
115*4882a593Smuzhiyun  * Returns The base
116*4882a593Smuzhiyun  */
cvmx_fpa_get_base(uint64_t pool)117*4882a593Smuzhiyun static inline void *cvmx_fpa_get_base(uint64_t pool)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	return cvmx_fpa_pool_info[pool].base;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /**
123*4882a593Smuzhiyun  * Check if a pointer belongs to an FPA pool. Return non-zero
124*4882a593Smuzhiyun  * if the supplied pointer is inside the memory controlled by
125*4882a593Smuzhiyun  * an FPA pool.
126*4882a593Smuzhiyun  *
127*4882a593Smuzhiyun  * @pool:   Pool to check
128*4882a593Smuzhiyun  * @ptr:    Pointer to check
129*4882a593Smuzhiyun  * Returns Non-zero if pointer is in the pool. Zero if not
130*4882a593Smuzhiyun  */
cvmx_fpa_is_member(uint64_t pool,void * ptr)131*4882a593Smuzhiyun static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
134*4882a593Smuzhiyun 		((char *)ptr <
135*4882a593Smuzhiyun 		 ((char *)(cvmx_fpa_pool_info[pool].base)) +
136*4882a593Smuzhiyun 		 cvmx_fpa_pool_info[pool].size *
137*4882a593Smuzhiyun 		 cvmx_fpa_pool_info[pool].starting_element_count));
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /**
141*4882a593Smuzhiyun  * Enable the FPA for use. Must be performed after any CSR
142*4882a593Smuzhiyun  * configuration but before any other FPA functions.
143*4882a593Smuzhiyun  */
cvmx_fpa_enable(void)144*4882a593Smuzhiyun static inline void cvmx_fpa_enable(void)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	union cvmx_fpa_ctl_status status;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
149*4882a593Smuzhiyun 	if (status.s.enb) {
150*4882a593Smuzhiyun 		cvmx_dprintf
151*4882a593Smuzhiyun 		    ("Warning: Enabling FPA when FPA already enabled.\n");
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/*
155*4882a593Smuzhiyun 	 * Do runtime check as we allow pass1 compiled code to run on
156*4882a593Smuzhiyun 	 * pass2 chips.
157*4882a593Smuzhiyun 	 */
158*4882a593Smuzhiyun 	if (cvmx_octeon_is_pass1()) {
159*4882a593Smuzhiyun 		union cvmx_fpa_fpfx_marks marks;
160*4882a593Smuzhiyun 		int i;
161*4882a593Smuzhiyun 		for (i = 1; i < 8; i++) {
162*4882a593Smuzhiyun 			marks.u64 =
163*4882a593Smuzhiyun 			    cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
164*4882a593Smuzhiyun 			marks.s.fpf_wr = 0xe0;
165*4882a593Smuzhiyun 			cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
166*4882a593Smuzhiyun 				       marks.u64);
167*4882a593Smuzhiyun 		}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 		/* Enforce a 10 cycle delay between config and enable */
170*4882a593Smuzhiyun 		__delay(10);
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	/* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
174*4882a593Smuzhiyun 	status.u64 = 0;
175*4882a593Smuzhiyun 	status.s.enb = 1;
176*4882a593Smuzhiyun 	cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /**
180*4882a593Smuzhiyun  * Get a new block from the FPA
181*4882a593Smuzhiyun  *
182*4882a593Smuzhiyun  * @pool:   Pool to get the block from
183*4882a593Smuzhiyun  * Returns Pointer to the block or NULL on failure
184*4882a593Smuzhiyun  */
cvmx_fpa_alloc(uint64_t pool)185*4882a593Smuzhiyun static inline void *cvmx_fpa_alloc(uint64_t pool)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	uint64_t address =
188*4882a593Smuzhiyun 	    cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
189*4882a593Smuzhiyun 	if (address)
190*4882a593Smuzhiyun 		return cvmx_phys_to_ptr(address);
191*4882a593Smuzhiyun 	else
192*4882a593Smuzhiyun 		return NULL;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /**
196*4882a593Smuzhiyun  * Asynchronously get a new block from the FPA
197*4882a593Smuzhiyun  *
198*4882a593Smuzhiyun  * @scr_addr: Local scratch address to put response in.	 This is a byte address,
199*4882a593Smuzhiyun  *		    but must be 8 byte aligned.
200*4882a593Smuzhiyun  * @pool:      Pool to get the block from
201*4882a593Smuzhiyun  */
cvmx_fpa_async_alloc(uint64_t scr_addr,uint64_t pool)202*4882a593Smuzhiyun static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	cvmx_fpa_iobdma_data_t data;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	/*
207*4882a593Smuzhiyun 	 * Hardware only uses 64 bit aligned locations, so convert
208*4882a593Smuzhiyun 	 * from byte address to 64-bit index
209*4882a593Smuzhiyun 	 */
210*4882a593Smuzhiyun 	data.s.scraddr = scr_addr >> 3;
211*4882a593Smuzhiyun 	data.s.len = 1;
212*4882a593Smuzhiyun 	data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
213*4882a593Smuzhiyun 	data.s.addr = 0;
214*4882a593Smuzhiyun 	cvmx_send_single(data.u64);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun /**
218*4882a593Smuzhiyun  * Free a block allocated with a FPA pool.  Does NOT provide memory
219*4882a593Smuzhiyun  * ordering in cases where the memory block was modified by the core.
220*4882a593Smuzhiyun  *
221*4882a593Smuzhiyun  * @ptr:    Block to free
222*4882a593Smuzhiyun  * @pool:   Pool to put it in
223*4882a593Smuzhiyun  * @num_cache_lines:
224*4882a593Smuzhiyun  *		 Cache lines to invalidate
225*4882a593Smuzhiyun  */
cvmx_fpa_free_nosync(void * ptr,uint64_t pool,uint64_t num_cache_lines)226*4882a593Smuzhiyun static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
227*4882a593Smuzhiyun 					uint64_t num_cache_lines)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	cvmx_addr_t newptr;
230*4882a593Smuzhiyun 	newptr.u64 = cvmx_ptr_to_phys(ptr);
231*4882a593Smuzhiyun 	newptr.sfilldidspace.didspace =
232*4882a593Smuzhiyun 	    CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
233*4882a593Smuzhiyun 	/* Prevent GCC from reordering around free */
234*4882a593Smuzhiyun 	barrier();
235*4882a593Smuzhiyun 	/* value written is number of cache lines not written back */
236*4882a593Smuzhiyun 	cvmx_write_io(newptr.u64, num_cache_lines);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun /**
240*4882a593Smuzhiyun  * Free a block allocated with a FPA pool.  Provides required memory
241*4882a593Smuzhiyun  * ordering in cases where memory block was modified by core.
242*4882a593Smuzhiyun  *
243*4882a593Smuzhiyun  * @ptr:    Block to free
244*4882a593Smuzhiyun  * @pool:   Pool to put it in
245*4882a593Smuzhiyun  * @num_cache_lines:
246*4882a593Smuzhiyun  *		 Cache lines to invalidate
247*4882a593Smuzhiyun  */
cvmx_fpa_free(void * ptr,uint64_t pool,uint64_t num_cache_lines)248*4882a593Smuzhiyun static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
249*4882a593Smuzhiyun 				 uint64_t num_cache_lines)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	cvmx_addr_t newptr;
252*4882a593Smuzhiyun 	newptr.u64 = cvmx_ptr_to_phys(ptr);
253*4882a593Smuzhiyun 	newptr.sfilldidspace.didspace =
254*4882a593Smuzhiyun 	    CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
255*4882a593Smuzhiyun 	/*
256*4882a593Smuzhiyun 	 * Make sure that any previous writes to memory go out before
257*4882a593Smuzhiyun 	 * we free this buffer.	 This also serves as a barrier to
258*4882a593Smuzhiyun 	 * prevent GCC from reordering operations to after the
259*4882a593Smuzhiyun 	 * free.
260*4882a593Smuzhiyun 	 */
261*4882a593Smuzhiyun 	CVMX_SYNCWS;
262*4882a593Smuzhiyun 	/* value written is number of cache lines not written back */
263*4882a593Smuzhiyun 	cvmx_write_io(newptr.u64, num_cache_lines);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun /**
267*4882a593Smuzhiyun  * Setup a FPA pool to control a new block of memory.
268*4882a593Smuzhiyun  * This can only be called once per pool. Make sure proper
269*4882a593Smuzhiyun  * locking enforces this.
270*4882a593Smuzhiyun  *
271*4882a593Smuzhiyun  * @pool:	Pool to initialize
272*4882a593Smuzhiyun  *		     0 <= pool < 8
273*4882a593Smuzhiyun  * @name:	Constant character string to name this pool.
274*4882a593Smuzhiyun  *		     String is not copied.
275*4882a593Smuzhiyun  * @buffer:	Pointer to the block of memory to use. This must be
276*4882a593Smuzhiyun  *		     accessible by all processors and external hardware.
277*4882a593Smuzhiyun  * @block_size: Size for each block controlled by the FPA
278*4882a593Smuzhiyun  * @num_blocks: Number of blocks
279*4882a593Smuzhiyun  *
280*4882a593Smuzhiyun  * Returns 0 on Success,
281*4882a593Smuzhiyun  *	   -1 on failure
282*4882a593Smuzhiyun  */
283*4882a593Smuzhiyun extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
284*4882a593Smuzhiyun 			       uint64_t block_size, uint64_t num_blocks);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun /**
287*4882a593Smuzhiyun  * Shutdown a Memory pool and validate that it had all of
288*4882a593Smuzhiyun  * the buffers originally placed in it. This should only be
289*4882a593Smuzhiyun  * called by one processor after all hardware has finished
290*4882a593Smuzhiyun  * using the pool.
291*4882a593Smuzhiyun  *
292*4882a593Smuzhiyun  * @pool:   Pool to shutdown
293*4882a593Smuzhiyun  * Returns Zero on success
294*4882a593Smuzhiyun  *	   - Positive is count of missing buffers
295*4882a593Smuzhiyun  *	   - Negative is too many buffers or corrupted pointers
296*4882a593Smuzhiyun  */
297*4882a593Smuzhiyun extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun /**
300*4882a593Smuzhiyun  * Get the size of blocks controlled by the pool
301*4882a593Smuzhiyun  * This is resolved to a constant at compile time.
302*4882a593Smuzhiyun  *
303*4882a593Smuzhiyun  * @pool:   Pool to access
304*4882a593Smuzhiyun  * Returns Size of the block in bytes
305*4882a593Smuzhiyun  */
306*4882a593Smuzhiyun uint64_t cvmx_fpa_get_block_size(uint64_t pool);
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun #endif /*  __CVM_FPA_H__ */
309